DTIC ADA548113: A Quaternary Decision Diagram Machine and the Optimization of Its Code

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39th International Symposium on Multiple-Valued Logic
A Quaternary Decision Diagram Machine and the Optimization of Its Code
TsutomuSasao 1,HirokiNakahara1,MunehiroMatsuura1
YoshifumiKawamura2,JonT.Butler3
1 KyushuInstituteofTechnology,Iizuka820-8502,Japan
2 RenesasTechnologyCorp.,Tokyo100-0004,Japan
3
NavalPostgraduateSchool,Monterey,CA93943-5121,USA
Abstract 2introducesamethodtorepresentmulti-outputlogicfunc-
tions by multi-valued decision diagrams. Section 3 intro-
We show the advantage of Quarternary Decision Dia- ducesbranchingprogrammachines: Itintroducesbotha4-
grams (QDDs) in representing and evaluating logic func- addressQDDmachineanda3-addressQDDmachine. The
tions. Thatis, we show howQDDs areusedtoimplement 3-address QDD machine requires less memorythanthe4-
QDD machines, which yield high-speed implementations. address QDD machine. Section 4 shows an optimization
WecompareQDDmachines withbinarydecisiondiagram problemofcodesfor3-addressQDDmachines. Section5
(BDD)machines, and show a speed improvement of 1.28- showstheexperimentalresults. Andfinally,Section6con-
2.02 times when QDDs are chosen. We consider 1-and 2- cludesthepaper.
address BDD machines, and 3- and 4-address QDD ma-
chines, and we show a method to minimize the number of
2 Representation of Multiple-Output Func-
instructions.
tions
1 Introduction 2.1 Multi-Valued Decision Diagrams
BranchingprogrammachinesforBDDshavebeenused Anarbitrarynvariablelogicfunctioncanberepresented
in control applications [2, 5, 7, 6]. Fast response is espe-
byabinarydecisiondiagram(BDD).EvaluationofaBDD
cially important in control applications in which there are requiresntablelook-ups. Fig. 2.1showsanexampleofan
usually hundreds of inputs. For such applications, a gen- MTBDD(multi-terminalbinarydecisiondiagram). Inthis
eralpurposemicroprocessor(MPU)cannotmeetthespeed
case, many outputs can be evaluatedat the same time. To
requirements. A branching program machine can be sev- furtherspeeduptheevaluation,amultiple-valueddecision
eraltimesfasterthananMPU:AnordinaryMPUrequires diagram (MDD) is used. In the MDD(k), k variables are
two or three machine instructions to read and test one in- grouped to form a 2k-valued super variable. To evaluate
putvariable,whilethebranchingprogrammachinerequires theMDD(k),weneedatmost(cid:1)n(cid:2)tablelook-ups[15,19].
k
justoneinstruction[3]. WhenthefunctionisrepresentedbyanMDD(k),theevalu-
In this paper, we present a Quarternary Decision Dia- ationofalogicfunctioncanbektimesfasterthanthecorre-
gram (QDD) to implement a branching program machine. spondingBDD1.Thus,alargerkyieldsafasterevaluation
Although the QDD machine requires longer instruction oftheMDD(k).Unfortunately,thesizeofmemorytorepre-
wordsthantheBDDmachine,theQDDmachineis1.3−2.0 sentanodeforanMDD(k)isproportionalto2k,asshown
times faster than the corresponding BDD machine. In the in Fig. 2.2. Formanybenchmarkfunctions, the total size
past,whenthepriceofmemorywashigh,16-bitcontrollers ofthememoryforanMDD(k)achievesitsminimumwhen
were popular [13, 25]. However, nowadays, the price of k = 2 [19]. Therefore, in logic evaluation, MDD(2)s are
memoryislower,anda32-bitorwiderarchitectureisoften
moresuitablethanBDDs. SincenodesinanMDD(2)have
usedtoincreasetheperformanceofcontrollers. So,inthis 4branches,itistermedaQuarternaryDecisionDiagram
paper, we show a method to increase the performance by (QDD).
increasingthenumberofbitsinaword.
The rest of this paper is organized as follows: Section 1ThisistrueonlywhentheMDD(k)andtheBDDarequasireduced.
0195-623X/09 $25.00 © 2009 IEEE 362
DOI 10.1109/ISMVL.2009.35
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A Quaternary Decision Diagram Machine and the Optimization of Its
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13. SUPPLEMENTARY NOTES
14. ABSTRACT
We show the advantage of Quarternary Decision Diagrams (QDDs) in representing and evaluating logic
functions. That is, we show how QDDs are used to implement QDD machines, which yield high-speed
implementations. We compare QDD machines with binary decision diagram (BDD) machines, and show a
speed improvement of 1.28- 2.02 times when QDDs are chosen. We consider 1-and 2- address BDD
machines, and 3- and 4-address QDD machines and we show a method to minimize the number of
instructions.
15. SUBJECT TERMS
16. SECURITY CLASSIFICATION OF: 17. LIMITATION OF 18. NUMBER 19a. NAME OF
ABSTRACT OF PAGES RESPONSIBLE PERSON

a. REPORT b. ABSTRACT c. THIS PAGE 8
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Standard Form 298 (Rev. 8-98)
Prescribed by ANSI Std Z39-18
ff
x N0 ff
1 x
x2 N1 x 0 1 1 x 0 X11,2 3 X1=(x1,x2)
0 2 1 0 21
N2 x3 0x31 0,1 X32 2 0,2 X2 1,3 X2=(x3,x4)
x x
N3 x4 x4 N4 x 1 x4 0 0 4 1x 1X3 0,2,30 X31,2,3 0X31,2,3 X3=(x5,x6)
f3 0 1 1 1 1 0x650100x5611 0x06 51 0,3X4 1,2 1 X40,2,3 X4=(x7,x8)
f 0 0 0 0 1 1
f21 0 0 1 1 1 1 0x7 1 0x71 0 1
f0 0 1 0 1 1 0x81 1x80
T0 T1 T2 T3 T4 0 BDD 1 MDD(2)
Figure2.1.ExampleofanMTBDD.
Figure2.3.ConversionofBDDtoMDD(2).
chitectureiswell-suitedforevaluatingMDDs,butiseasily
2 4 8 2k programmed.
k=1 k=2 k=3
3.1 2-Address BDD Machine
Figure2.2.NodesforMDD(k).
A branchingprogramforBDDs usesonlytwokindsof
instructions:
2.2 Optimization of MDDs B_Branch (ADDR0, ADDR1), INDEX
Output DATA, and GOTO ADDR.
In an MDD(k), the evaluation of an n-variable logic
functioncanbedonebyatmost(cid:1)n(cid:2)tablelook-ups.So,the Thefirstoneisthebinarybranchinstructionthatissim-
k
ilar to the computed GOTO statement of the FORTRAN
majorproblemistheminimizationofthenumberofnodes.
Ingeneral, it is notsoeasy toobtainanMDD(k)with the language: Ifthevalue ofthevariablespecifiedbyINDEX
isequalto0,thengotoADDR0,otherwisegotoADDR1.
minimumnumberofnodes.Thefollowingheuristicmethod
Thesecondoneperformstheoutputoperationfollowedby
isusedtoobtainnearminimalMDDs:
anunconditionalGOTOoperation.
1. MinimizethenumberofnodesoftheBDDbyaheuris-
ticmethod[21]. Example3.1 ConsidertheMTBDDshowninFig.2.1.The
2. Partition the input variables to generate an MDD(k) followingcodeevaluatestheMTBDD:
[22].
N0:B_Branch(N2,N1), X1
N1:B_Branch(N2,T4), X2
Fig.2.3showsanexampleofaconversionfromaBDDinto
N2:B_Branch(N3,N4), X3
anMDD(2).IntheaboveMDDs,weassumeeachgroupof
N3:B_Branch(T0,T1), X4
variableshasthesamesize.SuchMDDsarehomogeneous
N4:B_Branch(T2,T3), X4
MDDs. When the groups have different sizes, the MDD
T0:Output 0, and GOTO N0
isaheterogeneousMDD.Forsimplicity,inthispaper,we
T1:Output 9, and GOTO N0
consideronlyhomogeneousMDDs.
T2:Output 10, and GOTO N0
T3:Output 11, and GOTO N0
3 BranchingProgramMachine
T4:Output 15, and GOTO N0
Special machines to evaluate MDDs have been devel- Inthisexample,DATAinOutputDATAisthedecimalequiv-
oped[8,9,10].Unfortunately,theyareunsuitableforprac- alent of the function output values expressed in binary as
ticalapplications. Here, we considera machine whosear- f3,f2,f1,f0. (EndofExample)
363
PC Memory PC Memory
+1
COM INDEX ADDR0 ADDR1 COM INDEX ADDR1
Input Variables Input variables
xxx312 xi xxx312 xi
xn xn
Input selector Input selector
Figure3.1.2-addressBDDMachine. Figure3.2.1-addressBDDMachine.
Fig. 3.1showsthearchitectureofthe2-address BDDma- Fig.3.4showstheformatforthebranchinstruction.Fig.3.3
chine,whereonlythecircuitforthebranchingoperationis shows the architecture of the 4-address QDD machine,
shown. Thefirstfieldofthebranchinginstructionspecifies whereonlythecircuitforthebranchingoperationisshown.
thebranchcommand. The secondfield, INDEX,specifies The first field of the branching instruction specifies the
the index i of the input variables xi. It determines which branch command. Thesecondfield, INDEX,specifies the
variablestoselect. TheinputselectorinFig.3.1produces indexioftheinputvariableXi. Itdetermineswhichvari-
the value of the variable xi selecting the next branch ad- ablesto select. Inthe caseofa QDD,two consecutivebi-
dress. When xi = 0, ADDR0 is selected. Otherwise, nary variables are selected at a time. The input selector
ADDR1 is selected. The selected address is then loaded shown in Fig. 3.3 producesXi. The upper multiplexer se-
intotheprogramcounter(PC).Inthisway,thenextaddress lectsthevariable. WhenXi = (0,0),ADDR0isselected;
is specified. To reduce the widthof theinstructionwords, whenXi = (0,1),ADDR1isselected;whenXi = (1,0),
1-addressBDDmachinesshowninFig. 3.2havebeende- ADDR2isselected;andwhenXi = (1,1),ADDR3isse-
veloped[2,6,25,13].Inthiscase,whenthevaluespecified lected.Theselectedaddressisthenloadedintotheprogram
byINDEXis1,themachineworkssimilarlytothecaseof counter(PC).Inthisway,thenextaddressisspecifiedasa
the2-addressBDDmachine. Otherwise,thecontentofthe function ofINDEXi andthe inputvariable Xi. Notethat
programcounter(PC)isincrementedbyone,toaccessthe thisinstructionrequiresaratherlongword,whichwouldbe
next address. Inthis case, thesize of theinstructionword expensiveforembeddedapplications.
isreduced,butunconditionalGOTOinstructionsareneces-
Fig.3.5showstheformatfortheoutputinstruction. The
sary,asshownlater.
left field specifies the instruction type: Output. The mid-
dlefieldcontainstheaddresstowhichthisprogramshould
3.2 4-Address QDD Machine jump. The right field is the output value, as shown at the
bottomoftheQDD.
Byevaluatingtwobinaryvariablesandbyincreasingthe
number of branch addresses to four, we have a branch in-
3.3 3-Address QDD Machine
structionfora4-addressQDDmachine. Sinceitevaluates
twobinaryvariablesatatime,itcanreducetheevaluation
timetohalfthatofthe2-addressBDDmachine. Since the 4-address QDD instruction requires a long
word,wedevelopeda3-addressQDDmachine.Thebranch
Abranchingprogramfor4-addressQDDmachinescon-
instruction for the 3-address QDD machine contains only
sistsoftwokindofinstructions:
threeaddress fields. Forexample, considertheinstruction
Q_Branch(ADDR0,ADDR1,ADDR2,ADDR3),INDEX showninFig. 3.6. Thisinstructionissymbolicallydenoted
Output DATA, and GOTO ADDR by
364
Branch0 Index ADDR1 ADDR2 ADDR3
Figure3.6.BranchInstructionfora3-address
PC Memory
QDDMachine.
COM INDEX ADDR0 ADDR1 ADDR2 ADDR3
PC Memory
Input variables
xx1 Xi +1
2
x3 COM INDEX ADDR1 ADDR2 ADDR3
2
x
n
Input selector
Input variables
Figure3.3.4-addressQDDMachine. xxx312 Xi
xn 2
Branch Index ADDR0 ADDR1 ADDR2 ADDR3 Input selector
Figure 3.4. Branch Instruction for 4-address Figure3.7.3-addressQDDMachine.
QDDMachine.
Q_Branch(ADDR0,ADDR1,ADDR2,ADDR3),INDEX
Q_Branch(+1,ADDR1,ADDR2,ADDR3),INDEX.
canbesimulatedbythepairofinstructions:
Inthisinstruction,ADDR1,ADDR2,andADDR3arespec-
ified,butADDR0ismissing. ADDR0isreplacedby“+1”,
Q_Branch(+1,ADDR1,ADDR2,ADDR3),INDEX
which shows the next address of the current instruction.
GOTO ADDR0
Thisinstructionperformsthefollowingoperations:
• LetibethevaluespecifiedbyINDEX.If(i=0)then Note that the last instruction is an unconditional GOTO
goto the next address of the current instruction, else statement.Asshowninthenextsection,thenumberofun-
gotoADDRi. conditionalGOTOstatementscanbeminimizedbyanopti-
mizationalgorithm.Fig.3.7showsthearchitectureofthe3-
Lemma3.1 AnarbitraryQDDcanbeevaluatedbyapro-
addressQDDmachine,whereonlythecircuitforbranching
gramconsistingofthefollowinginstructions:
operations is shown. Consider the instruction in Fig. 3.6.
Q_Branch(+1,ADDR1,ADDR2,ADDR3),INDEX WhenthevaluespecifiedbyINDEXandtheinputvariables
GOTO ADDR isnon-zero,themachineworkssimilarlytothecaseofthe
Output DATA, and GOTO ADDR 4-addressQDDmachine. WhenthevaluespecifiedbyIN-
DEXandtheinputvariablesisequalto0,thecontentofthe
For example, the instruction for the 4-address QDD ma- programcounter(PC)isincrementedbyone,toaccessthe
chine nextaddress.
Intherealsystem, weusefourtypesofbranchinstruc-
tionsshowninFig.3.8.Todistinguishfourbranchinstruc-
Output Address OutputValues
tions, we use two additional bits in the instruction field.
However, as shown in the experimental results, by using
Figure 3.5. Output Instruction for a QDD Ma-
fourbranchinstructions, we can reduce the number of in-
chine.
structions andthetotalbitsize. So,thecostoftheseextra
bitsisfullycompensated.
365
Branch0 Index ADDR1 ADDR2 ADDR3 N0
X1
Branch1 Index ADDR0 ADDR2 ADDR3 0 1,2,3
Branch2 Index ADDR0 ADDR1 ADDR3 X2 X2 N1
Branch3 Index ADDR0 ADDR1 ADDR2 0 1,2,30 1,2,3
Figure3.8.FourTypesofBranchInstructions N2 X3 X3 N3
for3-addressQDDMachine. 0 1,2,30 1,2,3
0 1 2 3
T0 T1 T2 T3
4 OptimizationofCodesforQDDMachines
Figure4.1.QDDforExampleFunction.
Inthissection,weconsideramethodtoreducethenum-
berofinstructionsforQDDmachines.
Example4.1 ConsidertheQDDshowninFig. 4.1. Ithas
Definition4.1 Given the QDD and an order of the input
fivenon-terminalnodes,andfourterminalnodes.Whenthe
variables (e.g. x1,x2,..., and xn), the code size CSIZE
codeisgeneratedinthebreadth-firstorder,i.e.,intheorder
is the number of instructionsneededto compute the Deci-
sion diagram on a given machine. Let 4aQDDM denote ofX1,X2andX3,wehavethefollowing:
a 4-address QDD machine, and let 3aQDDM denote a 3- /** Code with Unconditional GOTO **/
addressQDDmachine. N0:Q_Branch(+1,N1,N1,N1),X1
Q_Branch(+1,N3,N3,N3),X2
Lemma4.1 LetNN bethenumberofnon-terminalnodes, GOTO N2
andletNT bethenumberofterminalnodesinaQDD.We N1:Q_Branch(+1,T3,T3,T3),X2
havethefollowingrelation:
GOTO N3
N2:Q_Branch(+1,T1,T1,T1),X3
CSIZE(4aQDDM)=NN +NT. (4.1)
GOTO T0
N3:Q_Branch(+1,T2,T2,T2),X3
(Proof)Ina4-addressQDDmachine,anon-terminalnode
GOTO T1
isrepresentedbyabranchinstruction,andaterminalnode
T0:Output 0, and GOTO N0
isrepresentedbyanoutputinstruction. (Q.E.D.)
T1:Output 1, and GOTO N0
Lemma4.2 LetNN bethenumberofnon-terminalnodes T2:Output 2, and GOTO N0
and let NT be the number of terminal nodes in a QDD. T3:Output 3, and GOTO N0
Let NU be the number of unconditional GOTOstatements
that are not part of output statements. Then, we have the Notethat,theaboveprogramhasfourunconditionalGOTO
followingrelations: statementsthatarenotpartofoutputstatements. However,
whenthecodeisgeneratedinthedepth-firstorder,ithasno
CSIZE(3aQDDM)=NU +NN +NT (4.2) unconditionalGOTOstatementsthatarenotpartofoutput
statements.:
0≤NU ≤NN (4.3)
/** Code without Unconditional GOTO **/
(Proof)Ina3-addressQDDmachine,anon-terminalnode N0:Q_Branch(+1,N1,N1,N1),X1
is representedbyeithera branchinstructionora paircon- Q_Branch(+1,N3,N3,N3),X2
sistingofabranchinstructionandanunconditionalGOTO Q_Branch(+1,T1,T1,T1),X3
statement. Also, a terminal node isrepresentedbyanout- T0:Output 0, and GOTO N0
putinstruction. Thus, thenumberofunconditional GOTO N1:Q_Branch(+1,T3,T3,T3),X2
statements is at most the number of non-terminal nodes. N3:Q_Branch(+1,T2,T2,T2),X3
(Q.E.D.) T1:Output 1, and GOTO N0
Inthecaseofa4-addressQDDmachine,thereisnocode T2:Output 2, and GOTO N0
optimizationproblem,i.e.,theinstructionscanbegenerated T3:Output 3, and GOTO N0
in any order. However, in the case of a 3-address QDD
machine,thelengthoftheprogramdependsontheorderof Note that the first four instructions correspond to the left-
instructions. most path from the root node to the terminal node T0.
366
Thenextthreeinstructionscorrespondtothepathfromthe statements; X = 00GOTOdenotes the numberofGOTO
the node N1, the node N3, and to the terminal node T1. statements,whenonlyonetypeofbranchinginstructionis
(EndofExample) used;Opt.GOTO=(Opt.Codes-QDD.Nodes)underQDD
denotesthenumberofGOTOstatements,whenfourtypes
The code optimization problem for a 3-address QDD ma-
branchinginstructionsareused;Aver.Inst.inQDDdenotes
chine can be reduced to a graph covering problem as fol-
theaveragenumberofinstructionstoevaluateaninputvec-
lows:
tor by a 3-address QDD machine; and Ratio denotes the
Definition4.2 ApathcoverofaQDDisasetofpathssuch value: (Aver. Inst. in1-addressBDDmachine)/(Aver. Inst.
thateverynodeintheQDDbelongstoexactlyonepath. A in3-addressQDDmachine).
minimalpathcoverisapathcoverwiththefewestpaths.
ApathinaQDDcanconsistofjustonenode. 5.2 Detail of the Experiment
Theorem4.1 An optimal code for a 3-address QDD ma-
Optimization of Decision Diagrams: First, the order-
chine corresponds to a minimal disjoint path cover of the
ing that minimizes the size of the MTBDD is obtained.
QDD.
Then,theinputvariablesarepartitionedintogroupsoftwo
(Proof) A path in a QDD corresponds to a sequence of variablesinthenaturalordertoobtaintheMTQDDs.
Q Branch instructions followed by an output instruction. OptimizationofCodes: Theorem4.1showshowtomini-
AsequenceofQ Branchinstructionswithoutanoutputin- mizethenumberofGOTOstatements.Thealgorithmgiven
struction requires an unconditional GOTO statement. By by[11]isonlyapplicabletotheprogramwithnodeswhose
Lemma 4.2, minimization of the number of unconditional in-degreesandout-degreesarebothtwo. So,wedeveloped
GOTOstatementsminimizesthecodesize. (Q.E.D.) ourownalgorithmtoobtainnearoptimalsolutionsforour
moregeneralcase.
5 Experiment andObservation
5.3 Observations
5.1 Benchmark Results
Fromthetable,wecanobservethefollowing:
To see the effectiveness of QDDs over BDDs, and the • ThenumberofnodesinQDDsissmallerthanthatof
effectiveness of the codeoptimization, we realizedcertain BDDs.
benchmark functions by BDDs and QDDs. First,we com- • Thenumberofinstructionsforthe3-addressQDDma-
pareQDDsandBDDswithrespecttothenumberofnodes. chinecanbeconsiderablyreducedbyanoptimization
Then, we convert these into code for BDD and QDD ma- algorithm.
chines,andcompareQDD’sandBDD’swithrespecttothe • For C432, in3, misex2, misj, and risc, the number of
numberofinstructions.
GOTOstatementsintheoptimizedQDDcodesiszero.
Table 5.1 shows the experimental results. Func. name
This means that optimal code is generated for these
denotes the name of the benchmark functions; # Inp. de-
functions. Also, forthesefunctions, optimalcodefor
notesthenumberofinputvariables;#Out.denotesthenum-
BDDmachinesaregenerated.
ber of outputs; BDD Nodes denotes the number of nodes
• signet requires manyGOTO statements in bothBDD
of the MTBDD including both terminal and non-terminal
andQDDmachines. ThenumberofGOTOstatements
nodes; Opt. Codes under BDD denotes the number of in-
foraBDDmachineisgivenby
structions of the optimized code for the 1-address BDD
(Opt.Codes)-(BDDNodes)=8671-7347=1324.
machine (near optimal solution); Term. Nodes denotes the
number ofterminalnodes; Aver. Inst. underBDD denotes • Opt.Codes,thenumberofinstructionsfora3-address
theaveragenumberofinstructionstoevaluateaninputvec- QDD machines is often larger than QDD Nodes, the
torbya1-addressBDDmachine;QDDNodesdenotesthe numberofinstructionsfora4-addressQDDmachine.
number of nodes of the MTQDD including both terminal The column headed by Opt. GOTO (=OPT. Codes -
andnon-terminalnodes, thatis the sameas the numberof QDD. Nodes) shows the extra GOTOs. Except for a
instructionsfora4-addressQDDmachine;X=00Codesun- fewfunctions,theextraGOTOsarerathersmall.
der QDD denotes the number of instructions in the code • Consider the value: (Sum of X=00 Codes)-(Sum of
for 3-address QDD machine, when only the first type of OptimalCodes)=28535-24528=4007. Thisshowsthe
instructioninFig. 3.8isused;Opt.CodesunderQDDde- total number of instructions reduced by using four
notesthenumberofinstructionsoftheoptimizedcodefor types of branch instructions, instead of using only
the3-addressQDDmachine,whenallfourtypesofinstruc- onetypeofbranchinginstructions. However,tospec-
tionsinFig.3.8areusedtominimizethenumberofGOTO ifyfourtypesofinstructions, we needtwo additional
367
Table5.1.NumberofNodesandCodeSizesforBDDMachineandQDDMachine.
BDD QDD
Func. # # BDD Opt. Term. Aver. QDD X=00 Opt. X=00 Opt. Aver. Ratio
Name Inp. Out. Nodes Codes Nodes Inst. Nodes Codes Codes GOTO GOTO Inst.
C432 36 7 1779 1779 128 19.10 1027 1408 1027 381 0 12.73 1.50
amd 14 24 206 206 84 5.63 164 171 164 7 0 3.47 1.62
apex2 39 3 335 363 8 6.66 231 332 265 101 34 4.99 1.33
apex4 9 19 749 750 319 8.24 600 639 601 39 1 4.61 1.79
chkn 29 7 220 241 28 7.01 157 215 172 58 15 5.16 1.36
duke2 22 29 636 637 255 6.36 546 594 547 48 1 4.09 1.55
gary 15 11 228 232 70 5.51 173 191 174 18 1 3.42 1.61
in0 15 11 195 200 52 5.02 145 170 148 25 3 2.92 1.72
in1 16 17 284 299 55 6.85 217 288 229 71 12 4.70 1.46
in2 19 10 291 296 73 3.98 219 262 225 43 6 2.60 1.53
in3 35 29 259 259 72 6.63 214 234 214 20 0 4.77 1.39
in4 32 20 607 611 178 4.69 491 569 495 78 4 3.44 1.36
in5 24 14 461 466 134 8.54 369 452 371 83 2 6.57 1.30
in6 33 23 4325 4338 1638 7.51 3546 3815 3555 269 9 5.88 1.28
in7 26 10 300 301 112 7.58 256 275 256 19 0 5.84 1.30
m181 15 9 222 222 84 6.80 196 217 196 21 0 4.71 1.44
misex2 25 18 113 113 35 4.97 91 96 91 5 0 3.60 1.38
misex3 14 14 2910 2975 1041 7.55 1773 2159 1773 386 0 4.05 1.86
misj 35 14 4656 4656 1408 14.12 3275 3828 3275 553 0 9.57 1.47
mlp6 12 12 5270 6062 1238 12.10 2582 2966 2694 384 112 5.98 2.02
risc 8 31 56 56 28 4.42 44 44 44 0 0 2.55 1.74
signet 39 8 7347 8652 128 18.23 5671 8374 6907 2703 1236 13.31 1.37
tial 14 8 697 790 49 12.05 388 552 466 164 78 6.37 1.89
vg2 25 8 131 135 24 7.65 89 110 91 21 2 5.62 1.36
x1dn 27 6 200 218 18 9.55 126 171 141 45 15 5.74 1.66
x6dn 39 5 214 231 28 4.14 159 215 177 56 18 2.74 1.52
x9dn 27 7 204 222 22 9.30 140 188 157 48 17 5.80 1.60
bits in the instruction field. Let w be the number of posed the use of four types of branch instructions. Also,
bits in a word in the 3-address QDD machine, where we considered a method to optimize codes for 3-address
onlyonetypeofbranchinginstructionis used. Then, QDDs. Thisisdifferentfromexistingmethodstooptimize
the merit of using four types of instructions is accu- the decision diagrams. For various benchmark functions,
rately expressed as: (Sum of X=00 Codes)×w-(Sum we optimized the codes, and showed the effectiveness of
ofOpt.Codes)×(w+2)=28535w−24528(w+2)= theapproach.
4007w−49056. Notethat,inmostcases,w >20,so ToshowtheusefulnessofQDDmachines, wehavede-
wecanconcludethattheuseoffourtypesofQ Branch veloped a parallel branching program machine (PBM128)
instructionsreducesthetotalnumberofbits. consists of 128 QDD machines and a programmable in-
• Thelast columnofthetableshowsthatthe3-address terconnection on the Altera’s Stratix II FPGA. We real-
QDDmachineis 1.28−2.02timesfasterthanthe1- ized many benchmark functions on PBM128, and com-
addressBDDmachine. NotethatforMLP6,theratio pared its memory size and computation time with the In-
isgreaterthan2. tel’sCore2Duomicroprocessor. PBM128requiresapprox-
imately a quarter of the memory for the Core2Duo, and
is 21.4-96.1 times faster than the Core2Duo. Details are
6 ConclusionsandComments
shownin[18].
In this paper, we considered a branching program ma-
Acknowledgments
chine to evaluate multiple-output logic functions. To in-
crease the speed of evaluation, we used QDDs instead of
BDDs.Toreducethememorysize,weused3-addressQDD This research is partly supported by The Japan Society
machines instead of 4-address QDD machines. We pro- forthe PromotionofScience(JSPS) GrantinAidforSci-
368
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