Digital Phase Accumulation for Direct Digital Frequency Synthesis

255 Pages·2013·3.02 MB·English

by  Joseph D. Cali

Digital Phase Accumulation for Direct Digital Frequency Synthesis
by
Joseph Dominic Cali
A dissertation submitted to the Graduate Faculty of
Auburn University
in partial fulfillment of the
requirements for the Degree of
Doctor of Philosophy
Auburn, Alabama
May 5, 2013
Keywords: DDS, DDFS, DCDO, DAC, Phase Truncation Errors, CORDIC
Copyright 2013 by Joseph Dominic Cali
Approved by
Fa Dai, Chair, Professor of Electrical and Computer Engineering
Richard Jaeger, Ginn Distinguished Professor of Electrical and Computer Engineering
Robert Dean, Associate Professor of Electrical and Computer Engineering
Stanley Reeves, Professor of Electrical and Computer Engineering
Abstract
This work explores direct digital frequency synthesis (DDFS) theory and design and its
application in radar systems. Though there is nothing particularly novel about DDFS in
general, recent designs have been revolutionized with the advancements in CMOS processes
and SiGe BiCMOS integration from 2000 to the current day. Many of the performance
limitations highlighted in early literature, such as the area and power of the sinusoidal read-
only memory (ROM), no longer apply to designs in modern integrated circuit (IC) processes.
Thedigitally-controlleddigitaloscillator(DCDO)oftheDDFScannowproducesignalswith
spectral purity far beyond the capabilities of the digital to analog converter (DAC). CMOS
miniaturization allows for high dynamic range sinusoids to be generated with CORDICs
instead of lossy compressed sine and cosine ROMs. Parallelization in the accumulator and
modulation paths eliminate the need for power hungry, current mode logic (CML) pipeline
accumulators. Noise shaping is better understood than at any point prior to this moment,
whichallowsustomitigatequantizationnoisethatarisesfromphaseoramplitudetruncation.
However, alarmingly few DDFS designs published in the past five years have taken note
of the radical shift in the design landscape. Of equal importance are the new challenges
that have arisen in small feature size geometries. In a way, this document is an attempt
to consolidate the state of the art in DDFS design and propose improvements from the
study. To this end, the dissertation is organized into two distinct sections, the DCDO and
the DAC. Digital phase accumulation and sinusoid generation are approached from number
theory and real analysis respectively. An exact computation of the spurs generated through
phasetruncationisdevelopedthatresultsinclosedformexpressionsfortheDCDOspectrum.
CurrentswitchesandarchitecturesforimprovedDACperformanceispresentedqualitatively.
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Acknowledgments
Journeying down the path of higher education can rarely be attributed to the will power
or foresight of the individual in pursuit. In recent years, I have appreciated the support of
the faculty and staff of Auburn University who have guided me through a challenging five
years of graduate school. In addition, I benefitted from the assistance of my fellow graduate
students with whom all my designs have interfaced in some manner. I acknowledge my major
advisor, Dr. Fa Dai for taking me on as a graduate student and funding eight integrated
circuit designs through my stint as a graduate student. I also must mention the members of
my committee Dr. Dean, Dr. Jaeger and Dr. Reeves for their specialized assistance through
many challenging design problems. I cannot fail to mention Dr. Niu, as his passionate and
skilled teaching of semiconductor physics from his deep knowledge of the subject has proven
helpful dozens of times on the job in my short time in the workforce.
There are countless teachers who from kindergarten through my undergraduate degree
at Louisiana State University (LSU) have devoted their energy and time to teaching me
and putting up with my relentless questions with regard to the “how’s” and the “why’s” of
this world. Without the prodding of my professors at LSU, I may have never considered
an advanced degree. Above these teachers stand the two greatest teachers in my life, my
mother and father, who have patiently raised me and provided emotional and financial
support throughout my academic journey. They sacrificed many conveniences for me to
attend a private school in preparation for college.
Lastly, I must thank my wife, Alison, for supporting me through the endless nights of
class work, the many weekends of research, my late night existential crises (now why am I
in graduate school again?), and tough medical challenges. She has certainly done more to
shape the outcome of this work than any other person in my life.
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Table of Contents
Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii
Acknowledgments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . viii
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiii
List of Theorems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xv
List of Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xviii
1 Introduction to Phase Accumulators . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Explanation of Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1.1 Number Theory Axioms and Notation . . . . . . . . . . . . . . . . . 6
1.1.2 Binary Arithmetic . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.2 Overview of Direct Digital Frequency Synthesis . . . . . . . . . . . . . . . . 13
1.3 Advantages of DDFS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.3.1 Digital Phase Modulation . . . . . . . . . . . . . . . . . . . . . . . . 20
1.3.2 Digital Frequency Modulation . . . . . . . . . . . . . . . . . . . . . . 22
1.3.3 Digital Amplitude Modulation . . . . . . . . . . . . . . . . . . . . . . 23
1.3.4 Fine Frequency Resolution and Fast Switching . . . . . . . . . . . . . 24
1.4 Summary of Contributions and Chapter Breakdown . . . . . . . . . . . . . . 24
2 Background of Phase Truncation Analysis . . . . . . . . . . . . . . . . . . . . . 26
2.1 Mehrgardt’s Analysis (1983) . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.2 Nicholas’s Analysis (1985) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.3 Jenq’s Analysis (1988) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.3.1 Jenq’s Observation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.3.2 Jenq’s Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
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2.4 Torosyan’s Analysis (2001) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3 Phase Accumulator Sequences from Number Theory . . . . . . . . . . . . . . . . 43
3.1 Phase Accumulator Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.2 Phase Accumulator Period . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.3 Truncated Phase Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.4 Relationships Between Sequences . . . . . . . . . . . . . . . . . . . . . . . . 62
3.5 Comments on Mathematical Structure . . . . . . . . . . . . . . . . . . . . . 66
4 Spectrum of Truncated Phase Sequences . . . . . . . . . . . . . . . . . . . . . . 68
4.1 Intuitive Understanding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
4.2 Characteristics of Truncated Phase Sequences . . . . . . . . . . . . . . . . . 72
4.3 Spectrum in the Presence of Phase Truncation . . . . . . . . . . . . . . . . . 79
4.4 Interpreting Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
4.4.1 Ideal SCMF Example . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
4.5 Numerical Verification of Theory . . . . . . . . . . . . . . . . . . . . . . . . 96
4.6 SFDR and SNR in the Presence of Phase Truncation . . . . . . . . . . . . . 96
4.6.1 SFDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
4.6.2 Worst Case SFDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
4.6.3 Spur Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
4.6.4 SNR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
4.7 Architecture Changes for Improved Spurious Response . . . . . . . . . . . . 106
4.7.1 Force Coprime FCWs . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
4.7.2 Phase Accumulator with Prime Number of States . . . . . . . . . . . 109
5 Parallelization of Phase Accumulator . . . . . . . . . . . . . . . . . . . . . . . . 111
5.1 Pipelined Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
5.2 Parallel Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
5.2.1 Prior Art . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
5.2.2 Derivation of LFM Enabled Architecture . . . . . . . . . . . . . . . . 117
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5.2.3 Area and Power Growth Analysis . . . . . . . . . . . . . . . . . . . . 119
5.2.4 Hardware Implementation . . . . . . . . . . . . . . . . . . . . . . . . 121
5.3 Multiplexer Upconversion Analysis . . . . . . . . . . . . . . . . . . . . . . . 123
5.4 Behavioral HDL Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
5.4.1 Problems with Existing Techniques . . . . . . . . . . . . . . . . . . . 126
5.4.2 A Simple Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
5.4.3 EDA Scripts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
5.4.4 Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
6 Radar Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
6.1 Previous DDFS Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
6.1.1 Sine Wave Symmetry . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
6.1.2 MTM DDFS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
6.1.3 BTM DDFS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
6.1.4 Output Response Analyzer . . . . . . . . . . . . . . . . . . . . . . . . 145
6.2 Overview of Basic Radar Theory . . . . . . . . . . . . . . . . . . . . . . . . 149
6.3 Overview of Stretch Processing . . . . . . . . . . . . . . . . . . . . . . . . . 150
6.3.1 Single Chip Radar . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
6.4 CORDIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
6.4.1 Basic Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
6.4.2 Conventional CORDIC . . . . . . . . . . . . . . . . . . . . . . . . . . 168
6.4.3 Optimizing the CORDIC Algorithm for DDFS . . . . . . . . . . . . . 170
6.4.4 Partial Dynamic Rotation CORDIC . . . . . . . . . . . . . . . . . . . 173
6.5 Stretch Processing DDFS Architecture . . . . . . . . . . . . . . . . . . . . . 175
6.5.1 Inverse Sinc Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
6.5.2 Radar Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
6.6 Design of 12-bit CMOS DAC . . . . . . . . . . . . . . . . . . . . . . . . . . 179
6.7 Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
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7 Digital-To-Analog Converters (DAC) . . . . . . . . . . . . . . . . . . . . . . . . 184
7.1 Basic Sampling Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
7.2 DAC Fundamentals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
7.3 DAC Performance Metrics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
7.3.1 Static DAC Performance . . . . . . . . . . . . . . . . . . . . . . . . . 196
7.3.2 INL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
7.3.3 DAC Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
7.4 Dynamic DAC Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
7.5 DAC Architectures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
7.5.1 R-2R DACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
7.5.2 Thermometer Coded and Segmented DACs . . . . . . . . . . . . . . . 209
7.5.3 Return-to-Zero (RTZ) . . . . . . . . . . . . . . . . . . . . . . . . . . 211
7.5.4 Translinear Output Buffers and Non-Linear DACs . . . . . . . . . . . 211
7.6 Current Steering Cell Architectures . . . . . . . . . . . . . . . . . . . . . . . 218
8 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
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List of Figures
1.1 Basic DDFS Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2 Gate Logic for One’s Complement . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.3 Phase Accumulator State Plots (Circle) . . . . . . . . . . . . . . . . . . . . . . 14
1.4 BPSK Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1.5 Simple Chirp Accumulator Diagram . . . . . . . . . . . . . . . . . . . . . . . . 22
1.6 10ns Chirp Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.1 Sawtooth Approximation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.2 Error Sequence Waveform Components . . . . . . . . . . . . . . . . . . . . . . . 33
3.1 Phase Accumulator State Plots . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.1 Spectrums from Two Adjacent FCWs . . . . . . . . . . . . . . . . . . . . . . . . 69
4.2 Simple Estimates for Worst Case SFDR due to Phase Truncation . . . . . . . . 71
4.3 Window Function from Example . . . . . . . . . . . . . . . . . . . . . . . . . . 94
4.4 Window Function from Example . . . . . . . . . . . . . . . . . . . . . . . . . . 95
4.5 Numerical Validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
4.6 Numerical Validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
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4.7 SFDR Function (Magnitude) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
4.8 Forcing Coprime FCWs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
4.9 Modification SFDR Improvement . . . . . . . . . . . . . . . . . . . . . . . . . . 108
4.10 Forcing Coprime FCWs (Modification) . . . . . . . . . . . . . . . . . . . . . . . 109
4.11 Mersenne Prime (17) Spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
5.1 Phase Accumulator with LFM . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
5.2 Block Diagram of Pipeline Accumulator . . . . . . . . . . . . . . . . . . . . . . 112
5.3 Block Diagram of Pipeline Accumulator with LFM . . . . . . . . . . . . . . . . 113
5.4 [1] Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
5.5 FSM Chirp-Enabled DDFS with Parallel Processing Path . . . . . . . . . . . . 116
5.6 Finite State Machine for Parallel Processing Path . . . . . . . . . . . . . . . . . 117
5.7 Proposed DDFS Using Novel Parallel Accumulator . . . . . . . . . . . . . . . . 118
5.8 Frequency and Phase Predictive Step . . . . . . . . . . . . . . . . . . . . . . . . 121
5.9 Parallel Phase Accumulator using Predictive Step . . . . . . . . . . . . . . . . . 122
5.10 4-to-1 Upconverting Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
5.11 CML Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
6.1 Quadrature, Quarter Sine Compression . . . . . . . . . . . . . . . . . . . . . . . 133
6.2 MTM DDFS Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
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6.3 MTM Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
6.4 MTM DDFS GDSII (130 µm BiCMOS) . . . . . . . . . . . . . . . . . . . . . . 138
6.5 BTM DDFS Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
6.6 Phase Accumulator State Plots . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
6.7 BTM ROM Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
6.8 BTM, CORIDC, ORA and DACs (130 µm BiCMOS) . . . . . . . . . . . . . . . 144
6.9 Galois 18-Bit LFSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
6.10 Phase Accumulator State Plots . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
6.11 BTM Simulation Versus Prediction . . . . . . . . . . . . . . . . . . . . . . . . . 147
6.12 Two Tone Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
6.13 ORA Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
6.14 Example of Stretch Processing Signals . . . . . . . . . . . . . . . . . . . . . . . 151
6.15 Radar-On-Chip Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
6.16 Die Photograph of RoC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
6.17 CORDIC Vector Rotations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
6.18 CORDIC Coverage Requirement . . . . . . . . . . . . . . . . . . . . . . . . . . 163
6.19 Conventional CORDIC Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
6.20 arctan Small Angle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
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