Digital logic using 3-terminal spin transfer torque devices

0.18 MB·

by  Benjamin Buford

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Digital logic using 3-terminal spin transfer torque
devices
Benjamin Buford, Albrecht Jander, and Pallavi Dhagat
School of Electrical Engineering and Computer Science
Oregon State University
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Corvallis, OR
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0 Email: [email protected]
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n
a
J A B
Abstract—We demonstrate for the first time that functionally
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complete digital logic can be created by using three terminal
1 S Terminal M
deviceseach consistingof amagnetictunneljunction(MTJ)and

spin transfer torque (STT) element with a shared free magnetic Pinned
l] layer. Rather than the output of devices being high or low STT Layer M S T
l voltagelevels,logicalstatesarerepresentedasoutputresistances Terminal
a Element
h which retain their state when unpowered. By cascading and
- clocking devices using a multi-phase clock, threshold logic can
s be used to implement functionally complete digital logic. Using Free Layer C
e this approach, a single device can act as an AND, NAND, OR, Tunnel Barrier
m
or NOR gate without the need for external circuitry. Required MTJ M
Pinned Layer
. device parameters and tolerances are discussed.
t
a Index Terms—Digital Logic, Spintronics, Tunnel Magnetore- S T
m T Terminal
sistance, Spin Valve, Spin Transfer Torque, Magnetic Tunnel
- Junction, Three Terminal Devices
d
Fig.1. Devicetopology(A)andproposedschematicsymbolfornon-inverting
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(B)andinverting (C)devices.
o I. INTRODUCTION
c
[ DIGITAL logic has traditionally been implemented us-
ingcomplementarymetal-oxide-semiconductor(CMOS) temperature),providesthebasisforthreeterminaldevicesthat
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transistors, but these devices are approaching their intrinsic can set the orientation of a magnetic free layer using current
v
2 scalability limit as device sizes approach the sub-nanometer through one current path, and can read the orientation of the
2 scale and off-state leakage current becomes intolerable [1], free layer through another [8], [10].
2 [2]. Spintronic devices show promise as an alternative to Here, we propose a method of cascading these three termi-
3 CMOS technology as most spintronic properties scale in- nal devices to implement digital logic. In this paper we will
.
1 versely with device size. Some spintronic logic devices, such discuss logic circuits created using the three terminal device
0 as spin accumulationmagnetologicgates [3], magnetic tunnel presentedbyBragancaetal.in[8],andshowninFigure1.This
1 junction logic devices [4], and domain wall logic devices [5] deviceconsistsofanMTJwhichsharesafreelayerwithaspin
1
have shown feasible approaches to spintronic logic, but rely transfertorqueelement,andhasathirdelectricalcontactmade
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v on inherently inefficient magnetic fields generated by traces to the free layer. The approach presented here will work for
Xi carryinghighcurrents.Recentlyanall-spinlogicdevice,which anythreeterminaldeviceexhibitingsimilarterminalbehavior.
relies only on spin polarized currents to set the orientation
r
a of magnetic layers, has been proposed [6]. This method II. PRINCIPLES OF OPERATION
eliminates the need for Amperian magnetic fields and instead For ease of discussing connectivity of devices we label
reliesonspintransfertorquetosettheorientationofmagnetic the three terminals T, M and S, corresponding to the tunnel
layers. junction, middle contact, and STT element respectively. We
Spin transfer torque (STT) was first presented in 1994 proposeconnectingdevicesina mannerseeninFigure2. The
by Slonczewski [7] as a method of setting the orientation T terminal acts as an output which has low or high output
of magnetization in a ferromagnet using a spin polarized resistance corresponding to the orientation of the free layer.
current. Spin transfer torque induced switching requires high TwoclocklinesareconnectedtotheMterminalsofalternating
current densities of up to 107 A/cm2, and has shown a giant devices, but only one clock line is active at a time while the
magnetoresistiveeffectontheorderof10%[8].Theefficiency other serves as a ground connection. When a device is being
of spin transfer torque scales inversely with device size. clockedwithapositivevoltage,currentflowsthroughtheSTT
Spin transfer torque,combinedwith the ability of magnetic element from the M terminal to the S terminal and then is
tunnel junctions (MTJs) to demonstrate the high tunneling dividedbetweena shuntresistor to groundandthe T terminal
magnetoresistance (TMR) effects (of up to 604% [9] at room ofthepreviousstage.Thiscausesthemagnitudeofthecurrent
2
A
Consider the buffer Q1 shown in Figure 2 which can be
Clk 0 C thought of as two resistors Rsm1 and Rtm1 corresponding to
Clk 1 the STT element (S to M terminals) and tunnel junction (T
Q0 Q1 Q2 to M terminals), where Rtm1 can take on a high (RAP) or
V
In Out ch Clk 0 low (RP) resistance state. The currents IMS and IMT, given
0
by (1) and (2), are of particular interest, as excessive IMT
VVcl causes junction breakdown but IMS needs to be sufficiently
B ch Clk 1 largetoswitchtheorientationofthefreelayer.Forsimplicity,
0
Clk 0 V we assume the first order approximation that the free layer
cl
Clk 1 magnetization will switch orientation if a sufficient current is
t t appliedfor a defined pulse time, th or tl. Thisis equivilentto
R R R R l h
In tm0 sm1 tm1 sm2 Out assuming a charge threshold Qth is required for switching.
Rs1 Rs2 Vclk
IMS = (1)
Rsm1+(Rtm0||Rs1)
Fig. 2. A) Three buffers chained together and driven by two clock lines. Vclk
B) The schematic decomposed into junction resistances. Only components IMT = Rtm1+(Rsm2||Rs2) (2)
involved during the operation of Q1 have been highlighted and labeled. C)
Clock timing diagram. Each clock line is first pulsed low during the preset During the preset pulse the resistance Rs1 and voltage Vch
phase,thenpulsedhighduringtheevaluatephase.Adjacentstagesareclocked
musthavebeenchosentomeettwoconditions.First,thepreset
alternately toavoidlossofdataduringthepresetduringeachclockcycle.
pulse must cause a large enough charge to pass through the
STT element (Rsm1) to unconditionally set Rtm1 to a high
which flows through the STT element to be dependenton the state. Second, the charge passing through Rsm2 must be low
output resistance of the previous stage. Threshold logic can enough to not change its state.
be implemented if the variation of current corresponding to Duringtheevaluatephase,switchingmustonlyoccurwhen
high and low output of the previous stage is large enough to theoutputofthepreviousstageisahighresistance.Therefore,
make the difference between reliably switching and reliably theevaluatepulsemusteitherbealoweramplitudeorashorter
not switching the magnetic orientation of the free layer. duration than the preset pulse. This guarantees that as long
as adjacent devices were not altered during the preset phase,
Due to the inherent hysteresis in magnetic systems, con-
siderations must be made to allow for digital logic to be it will not be altered during the evaluate phase. Additionally
implemented without feedback; that is, when clocked, the |IMS ∗ tl| must be below Qth when Rtm0 is in its high
output of a device should only depend on the output of the resistance state and above Qth when Rtm0 is in its low
previous stage and not its own previous state. Additionally, resistance state.
the state of the previous device should remain unchanged. To When considering the worst case device state, these condi-
accomplish this we use a two phase clock to first preset, and tionsyieldthefollowingfourinequalitiesthatmustbemetfor
then to evaluate the state of the device. One clock is first proper device operation:
pulsed low to unconditionally set the orientation of the free
Vcl∗tl
layer to the anti-parallel state (preset), then pulsed high to >Qth (3)
Rsm1+(RAP||Rs1)
conditionally set the orientation to a parallel state only if the
previous stage had a low resistance output (evaluate). The |Vch|∗th
magnitudeofthepresetpulseislargerthanthatoftheevaluate <Qth (4)
Rsm1+(RAP||Rs1)
pulse to induce a sufficient switching current regardless of
the output resistance of the previous stage. Sequential stages |Vch|∗th
of logic are then clocked in an alternating fashion (Figure 2 Rsm1+(RP||Rs1) >Qth (5)
C). Since the switching characteristics of spin transfer torque
elementsaretypicallyasymmetric,i.e.switchingthefreelayer Vcl∗Rs2∗tl
<Qth (6)
from anti-parallel to parallel magnetization takes less current RP ∗Rs2+RP ∗Rsm2+Rs2∗Rsm2
than switching from parallel to anti-parallel, the difference in
If these conditions are met, the preset pulse will set the
clock voltage magnitude may be unnecessary.
outputofQ1toahighresistance,andifandonlyiftheoutput
ofQ0isalowresistancetheevaluatepulsewillsettheoutput
of Q1 to a low resistance.
A. Single Input Gates
The buffer and inverter are topologically identical; an in-
B. Multiple Input Gates
verter is simply a buffer with the magnetic orientation of
one the pinned layers reversed during fabrication. If the Like the buffer and inverter, an AND and NAND gate can
MTJ contains the reversed pinned layer it allows anisotropic each be implemented using a single device and differ from
switchingcharacteristicstobehavesimilarlyforbothinverting eachotheronlybythe orientationofa pinnedlayer. Sincethe
and non-invertingdevices. devicestateisdeterminedbyoutputresistanceoftheprevious
3
Clk 0
Clk 1 045+!
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A
& &
6+1232*
! !
C
045+&
& & &
0+1232*
B
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Fig.3. SchematicforaNANDgatewithinputsAandB.Threeperipheral
Fig.4. SimulatedtimingdiagramforaNANDgateusingidealized devices
buffershavebeenaddedtoshowconnectivity toadjacent stages.
whichhaveanoutputthatinstantlyswitchesresistancesaftercurrentthrough
theSTTelementexceeds adefinedthresholdforadefinedperiodoftime.A
freelayerorientationcreatingalowoutputresistanceisarbitrarilyrepresented
stage, thresholdlogic canbe implementedby puttingmultiple asalogical 0,andahighoutputresistance corresponds toalogical 1.
input devices in parallel, as shown in Figure 3.
By adjusting the resistance of the attached shunt resistor
the shunt resistor must be decreased to allow a much larger
the resistance threshold can be modified to allow the device
bias which is again proportionalto the amountof fanout. If a
to switch during the negative clock pulse when either or both
largefanoutis required,device size can be increasedto lower
of the inputs are low resistance. A simulated timing diagram
the MTJ resistance while keeping the same TMR value. This
of a NAND gate is shown in Figure 4. Consider the periods
increasesthe currentthe MTJ is able to sink withoutdamage.
of time where Clk 1 is active; During the preset phase at t=1
ns, Clk 1 is pulled low causing a sufficiently large IMS in
III. DEVICE PARAMATERSCALING AND TOLERANCE
the STT element of the NAND gate to cause the free layer to
switch to a state anti-parallel to the pinned layer of the STT One advantage of magnetic based logic over traditional
element.Sincethisisaninvertingdevice,thefreelayerisnow CMOSlogicisthatenergyrequirementsscalewithdevicesize;
parallel to the pinned layer of the MTJ and the output is low Since device switching is dependent on a current exceeding
resistance, or logical 0. Next, during the evaluate phase, Clk a critical current density threshold, the required switching
1 is pulled positive, but to a lesser voltage magnitude. Since current is proportional to the STT element junction area.
the resistance of both devices in the previous stage is high, Similarly,theappliedvoltagerequiredtoachievetheswitching
IMS is smaller and insufficient to switch the state back to a current density is proportional to the resistance of the junc-
high resistance, leaving the output as a logical 0 and ready tions, and thus scales inversely with device size.
to be read by the next gate in series. At t=3 ns the device For use in digital logic device quality can be characterized
is already in a low resistance state, so the preset pulse does to first order by the switching current density threshold, the
notchangethe state of the device.Theevaluatepulse att=3.5 junction area for both the tunnel junction and spin transfer
ns creates a current large enough to toggle the device as the torqueelement,theTMRratio,andtheresistanceareaproduct
output resistances of both devices in the previous stage are (RAP) of the tunnel junction when it is in a low resistance
low. state. While most of these device parameters are fabrication
An OR or NOR gate can be created by adjusting the process dependentand currentlycannot be controlledto great
shunt resistor, effectively shifting the current bias point to precision, overall logic operation can be designed to work
cause the evaluate phase to switch switch device state only for a wide tolerance of device characteristics by carefully
when both inputs have a low resistance. Threshold logic can selecting the shunt resistor value as well as the amplitude
be implemented by varying the device size to scale output of the voltage pulses on the clock lines in order to expand
resistances. the bounds on the switching current given in inequalities 3-
6. The following section will be a discussion on how these
parameters should be optimized to increase the tolerance to
C. Fanout
variationsin parameterswhile decreasingoverallpowerusage
Astheoutputstateofadeviceisexpressedasanresistance, for the discussed magnetic logic implementation.
fanout is only limited by the amount of current the MTJ can To analyze the effects various device parameters have on
sink without damaging it. Having more than one gate con- logic operation we first assume all parameters are equal to
nectedtotheoutputofasingledevicerequiresthatthedevice those presented in [8], then sweep a single device parameter
mustsinkcurrentdirectlyproportionalto the fanout.Since all andselectanoptimalshuntresistor(Rs)andclockvoltagesto
of the devices in the fanout must be clocked synchronously, maximizethedifferenceinboundsontheswitchingcurrentin
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4.!"/!0 IV. CONCLUSION
We have presented a method for implementing arbitrary
->3.!"/!0 digital logic using a three terminal device consisting of back-
= to-back STT junction and MTJ. The implementation requires
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+&6*2.!"/!0 $’.)?@?&#*A78’6B7 two out of phase and multi-level clock lines which supply all
)(’ power to the devices. Digital information is stored as solid-
87;< 3", state magnetization of magnetic layers, and is read out as
&871.!"/!0 2", variable conductances when succeeding devices are clocked.
;
&:9 To improve the efficiency of these devices device fabrication
8760.!"/!0 1", must be perfected to create three terminal devices with low
5
0", junction resistance but high TMR ratios and well defined
!.!"/!0 switching current thresholds. As fabrication technology im-
!",
proves, this approach to implementing digital logic has the
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opportunitytoprovidelowpower,highspeed,andnon-volatile
#$%&%’()*&+,-
logic operations.
Fig.5. EnergyperoperationforvariousMTJTMRratioswheretheapplied
clock voltage and shunt resistor value are selected for various allowable
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STT element RAP. The effect of TMR ratio behaves non-
linearly, and is shown in Figure 5. The dotted line shows the
energyrequiredassumingshuntresistorandvoltageamplitude
are selected to allow for maximum process variation. If the
process can guarantee parameters lie within tighter bounds,
optimizationsto the shunt resistance can be made to decrease
overall power consumption.
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100 Ωµm2, but the exact value is dependent on other device
properties.