Digital logic design using Verilog : coding and RTL synthesis

607 Pages·2022·20.357 MB·English

by  Vaibbhav Taraate

Vaibbhav Taraate
Digital Logic
Design Using
Verilog
Coding and RTL Synthesis
Second Edition
Digital Logic Design Using Verilog
Vaibbhav Taraate
Digital Logic Design Using
Verilog
Coding and RTL Synthesis
Second Edition
123
Vaibbhav Taraate
1 RupeeST (Semiconductor
Training@ Rs.1)
Pune,Maharashtra, India
ISBN978-981-16-3198-6 ISBN978-981-16-3199-3 (eBook)
https://doi.org/10.1007/978-981-16-3199-3
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Dedicated to my Inspiration
Bharat Ratna Lata Mangeshkar
&
Bharat Ratna Sachin Tendulkar
For giving me real happiness and many
happy moments!
Preface
IamdelightedtohavethesecondeditionoftheDigitalLogicDesignUsingVerilog
book.Duringthepastfiveyears,thefirsteditionhasmorethan80Kdownloadsand
then I thought to work on the second edition of the book.
This edition includes the Verilog RTL design and verification using the
Verilog-2005 style constructs. Throughout this book, I have used the constructs
from the stable release of Verilog, that is, IEEE 1364-2005. The keywords are
highlightedusingbold bluecolor,andthisbookisusefultoRTLdesignengineers
who wish to pursue their career in RTL design, FPGA design, and ASIC design.
Even the performance improvement of the design and overall design improvement
techniques are included in this edition!
For the synthesis of the RTL designs, I have used Xilinx Vivado and ISE 14.7.
The readers can go to www.xilinx.com to download the EDA tool, and even they
can purchase the Xilinx FPGA boards and tools to implement the products and
ideas.
The book has 25 chapters and is mainly useful to understand about the RTL
design concepts, synthesizable and non-synthesizable Verilog constructs, and
basics of testbenches to check for the functional correctness of the design.
ThebookevencoverstheadvancedconceptsusedintheASICdesignsynthesis,
with the low power and multiple clock domain design concepts.
Chapter 1 “Introduction” describes about the evolution of logic design, design
methodology, and the basics of Verilog. The chapter discusses basics of Verilog
Simulation and synthesis flow.
Chapter 2 “Concept of Concurrency and Verilog Operators”, for any language,
the operator plays an important role. The Verilog supports various operators, and
the chapter discusses the use of these operators in the RTL design.
Chapter 3 “Verilog Constructs and Combinational Design-I” discusses the
combinational logic design using the synthesizable Verilog constructs. Also, it
discusses the practical and real-life scenarios, useful while implementing combi-
national designs.
Chapter 4 “Verilog Constructs and Combinational Design-II” discusses RTL
design for few of the arithmetic resources and the code converters.
vii
viii Preface
Chapter5“MultiplexersasUniversalLogic”discussestheefficientRTLcoding
for multiplexers and parallel versus priority logic.
Chapter 6 “Decoders and Encoders” discusses the efficient RTL coding for
decoders and encoders. The RTL design strategies for these combinational design
elements are discussed using the synthesizable constructs.
Chapter7“EventQueueandDesignGuidelines”discusseseventqueueandfew
important design and coding guidelines for the combinational logic design.
Chapter 8 “Basics of Sequential Design Using Verilog” is useful to understand
abouttheRTLdesignforthelatchesandflip-flop.Theconceptofthesynchronous
and asynchronous reset is also discussed.
Chapter 9 “Synchronous Counter Design Using Synthesizable Constructs”, the
RTL design of various synchronous counters using the synthesizable constructs is
discussed. The chapter discusses the RTL design, simulation, and synthesis
concepts.
Chapter10“RTLDesignofRegistersandMemories”isusefultounderstandthe
RTL design techniques and strategiestocode theRTLfor registers, shift registers,
and memories.
Chapter 11 “Sequential Circuit Design Guidelines” discusses the sequential
design guidelines which need to be followed while coding an efficient RTL using
synthesizable Verilog constructs.
Chapter 12 “RTL Design Strategies for Complex Designs” discusses the use of
synthesizable Verilog constructs to implement the complex designs for the desired
functionality.
Chapter13“RTLTweaksandPerformanceImprovementTechniques”discusses
thearea,speed,andpowerimprovementbasicsandisusefulduringtheRTLdesign
and synthesis stage to improve the design performance.
Chapter 14 “Finite State Machines Using Verilog”, the RTL design for the
MooreandMealymachineisdiscussed.TheFSMencodingstylesarebinary,gray,
and one-hot encoding and are discussed in this chapter.
Chapter 15 “Non-synthesizable Verilog Constructs and Testbenches” discusses
the inter-, intra-delay assignments and other non-synthesizable constructs useful
during the testbenches. The chapter is useful to understand about the
non-synthesizableconstructsandhowtocheckforthefunctionalcorrectnessofthe
design.
Chapter 16 “FPGA Architecture and Design Flow” discusses the FPGA archi-
tecture, design flow, and the simulation using the FPGA.
Chapter 17 “FPGA Design and Guidelines” discusses the design guidelines for
FPGA-based designs. How to use thedesign guidelines is explained with the RTL
designs coded using the synthesizable Verilog constructs.
Chapter18“ASICDesign”discussestheASICtypesandbasicsofASICdesign
flow.
Chapter 19 “ASIC Synthesis and SDC Commands” discusses the ASIC syn-
thesis and important SDC commands used during synthesis.
Chapter 20 “Static Timing Analysis” discusses the STA concepts useful during
the timing analysis and during the timing closure.
Preface ix
Chapter 21 “Design Constraints And Optimization” discusses the design con-
straints and optimization using Synopsys DC.
Chapter 22 “Multiple Clock Domain Design” discusses the multiple clock
domain design techniques and the control and data path synchronizers and their
use!
Chapter 23 “Case Study: FIFO Design” is useful to understand the FIFO depth
calculations and discusses the FIFO design, simulation of FIFO, and synthesis.
Chapter24“LowPowerDesign”discussesthelowpowerdesigntechniquesand
the need of Unified Power Format. This chapter is also useful to understand about
the UPF concept and its use.
Chapter 25 “System-On-Chip (SOC) Design”, the SOC consists of many
complex blocks like processors, arbiters, memories, and peripherals. These blocks
are discussed in this chapter. This chapter even focuses on the generalized SOC
architecture and the SOC design flow.
The book includes many practical examples to understand how to code an
efficientRTLusingVerilog.Thebookisalsousefultounderstandthesynthesizable
designs and frequent issues in the RTL design and how to overcome them. The
book even covers the performance improvement using RTL tweaks and the ASIC
and FPGA synthesis for a better understanding.
This book is useful to the engineering students, VLSI beginners, and profes-
sionals who wish to implement synthesizable design using Verilog!
Pune, India Vaibbhav Taraate
Acknowledgements
The second edition of this book is originated due to my extensive work in FPGA
and ASIC design from the year 2000. The journey to design the architectures will
continueinthefuturealsoandwillbehelpfultomanyprofessionalsandengineers.
This book is possible due to the help of many people. I am thankful to all the
participants to whom I taught the subject digital design and RTL design using
Verilog in various multinational corporations. I am thankful to all those entrepre-
neurs,design/verificationengineers,andmanagerswithwhomIworkedinthepast
almost around 20 years.
I am thankful to my dearest friends for their constant support. I am especially
thankful to my friends and well-wishers and family members. Special thanks to
Neeraj and Deepesh for their best wishes and for their valuable help during the
manuscript work.
The book is possible due to the best wishes and constant encouragement of
Raghu, Satya, Venky, Srinath, Rohit, Acharya, Suresh, Nitin, Rohit, Amit, Anil,
Ashok, Deepak, Shrinivas, Sunil, Madhuseth, Sanjuseth, and Rahul. I am thankful
to my dearest sister Manisha, Dhanashree, Sharmistha, Neha, Annu, Anjali,
Vaishali, Anjani, and Esha for their faith and belief on me and for best wishes.
Finally, I am thankful to the Springer Nature staff, especially Swati Meherishi,
MuskanJaiswal,AshokKumar,Silky,RiniChristy,andUmamageshfortheirgreat
support during various phases of the manuscript.
Special thanks in advance to all the readers and engineers for buying, reading,
and enjoying this book!
xi
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Evolution of Logic Design. . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 System and Logic Design Abstractions. . . . . . . . . . . . . . . . . . 3
1.2.1 Architecture Design . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2.2 Micro-architecture Design . . . . . . . . . . . . . . . . . . . . 3
1.2.3 RTL Design and Synthesis . . . . . . . . . . . . . . . . . . . 4
1.2.4 Switch Level Design. . . . . . . . . . . . . . . . . . . . . . . . 4
1.3 Integrated Circuit Design and Methodologies . . . . . . . . . . . . . 4
1.3.1 RTL Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.3.2 Functional Verification . . . . . . . . . . . . . . . . . . . . . . 5
1.3.3 Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.3.4 Physical Design . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.4 Verilog as Hardware Description Language . . . . . . . . . . . . . . 6
1.5 Verilog Design Description . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.5.1 Structural Design . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.5.2 Behavior Design. . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.5.3 Synthesizable Design . . . . . . . . . . . . . . . . . . . . . . . 14
1.6 Few Important Verilog Terminologies . . . . . . . . . . . . . . . . . . 16
1.7 Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.8 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2 Concept of Concurrency and Verilog Operators. . . . . . . . . . . . . . . 21
2.1 Use of Continuous Assignment to Model Design . . . . . . . . . . 21
2.2 Use of always Procedural Block to Implement
Combinational Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.3 Concept of Concurrency . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.4 Verilog Arithmetic Operators. . . . . . . . . . . . . . . . . . . . . . . . . 25
2.5 Verilog Logical Operators . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.6 Verilog Equality and Inequality Operators . . . . . . . . . . . . . . . 28
2.7 Verilog Sign Operators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
xiii