Digital Logic Design Using Verilog: Coding and RTL Synthesis

431 Pages·2016·56.02 MB·English

by  Vaibbhav Taraate (auth.)

Vaibbhav Taraate
Digital Logic
Design Using
Verilog
Coding and RTL Synthesis
Digital Logic Design Using Verilog
Vaibbhav Taraate
Digital Logic Design Using
Verilog
Coding and RTL Synthesis
123
Vaibbhav Taraate
SemiconductorTraining @Rs.1
Pune,Maharashtra
India
ISBN978-81-322-2789-2 ISBN978-81-322-2791-5 (eBook)
DOI 10.1007/978-81-322-2791-5
LibraryofCongressControlNumber:2016936278
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Dedicated To the Supreme Lord
of Intelligence
And
To All Students and Readers!
Preface
Today’scenturyiseraofminiaturizationandhigh-speedchips,andcomplexASICs
are designed in lesser time as compared to before. The technology evolution from
1990 has opened up a new paradigm for ASIC designers. Customers are always
expecting the speedy delivery of the ASIC products and it always accumulates the
good amount of pressure to come up with the high-performance design using less
number of resources.
The evolution in the process node technology in the past decade has started the
real evolution in the semiconductor industry! Many new design techniques and
flows got evolved and stabilized in the past decade. Many EDA tool companies
help designers to complete the design in shorter time span.
In today’s industrial scenario, designer doesn’t spend more time to draw the
schematictodesignthedigitallogiccircuits.TheEDAtoolshaveenabledthebest
design practices by using hardware description languages such as VHDL and
Verilog. The synthesis tools are used primarily to convert the HDL into the
equivalent logic structure or gate level netlist. The latest EDA tool features have
also improved the productivity and efficiency of the design team!
Thebookisorganizedintothreesections;thefirstsectionconsistsofChaps.1–9
and describes about the digital logic design and synthesizable Verilog RTL.
Section I is organized in such a way that reader will be able to have better
understandingofbasicsofdigitallogicandsynthesizableRTL.Thissectionwillbe
helpful for the reader to understand the Verilog HDL constructs, hardware infer-
ence,simulationconceptsanddesignguidelinesforsimpletocomplexdesigns.For
the better understanding of the reader, few practical scenarios are included in this
section.
Chapter 1 discusses about the evolution of the logic design, logic design
abstraction levels, IC design methodologies and flow, Verilog Module declaration,
and different design styles. This chapter discusses about the simulation and syn-
thesis flow for the Verilog RTL. Even this chapter discusses about the key verilog
HDL features.
vii
viii Preface
Chapters 2 and 3 describe about the combinational logic design and synthesiz-
able RTL. These chapters also focus on the practical issues and scenarios while
designing the combinational logic using Verilog RTL.
Chapter4discussesonthekeyVerilogcodingguidelinesandtheroleofVerilog
in writing an efficient RTL for combinational design.
Chapter 5 discusses about the sequential logic design and covers most of the
simple to complex practical design scenarios. This chapter also deals with the
synthesizable sequential design issues, timing diagrams, and simulation of the
design.
Chapter6discussesonthekeyVerilogcodingguidelinesandtheroleofVerilog
in writing an efficient RTL for sequential design.
Chapter 7 describes about the efficient RTL coding for a few complex density
designs and also gives information about the synthesizable results and the key
practical scenarios for the design.
Chapter 8 deals with FSM and design of an efficient FSM using the suitable
FSM encoding styles.
Chapter 9 describes the simulation concepts and PLD based design. Even this
chapter describes about the design guidelines while using PLDs.
Section II consists of Chaps. 10–12 and mainly deals with the logic synthesis,
the static timing analysis, and the constraining ASIC designs. This section is
organizedinsuchawaythatreadercanhavebetterunderstandingofsynthesizable
Verilog RTL and constraining designs for given specifications. This section also
deals with the static timing analysis and practical issues in performance improve-
ment for the design.
Chapter 10 discusses about the logic synthesis, ASIC design flow, design con-
straints, and gate level netlist.
Chapter 11 describes the static timing analysis and the timing reports and
analysis for complex RTL designs. This chapter also deals with the practical few
practical scenarios in the design and performance improvement technique.
Chapter 12 discusses about the different design constraints and how to tweak
architecture, microarchitecture, and RTL to improve the design performance. This
chapter also deals with the DRC, optimization and performance improvement
scenarios for better understanding of the design constraints.
SectionIIIconsistsofChaps.13–15andmainlydiscussesontheadvancedRTL
design concepts such as multiple clock domain designs, need of synchronizers,
clockdomaincrossing,lowpowerdesigns,andSOC-baseddesignsandchallenges.
Every chapter in this section discusses about the key practical scenarios using the
efficient Verilog RTL.
Chapter 13 describes about the multiple clock domain designs and the syn-
chronizers and their need. This chapter also focuses on synchronous and asyn-
chronous FIFO buffers and RTL design using Verilog and concludes with a case
study.
Chapter14discussesonmostofthelowpowerdesigntechniquesandthegoalof
designerstoimplementthelowpowerdesigns.Thischapteralsodealswiththelow
power design architecture and power sequencing for the low power designs.
Preface ix
Chapter15focusesonthereal-lifeSOC-baseddesignsandtheroleofVerilogin
implementing the SOC-based designs.
The book consists of many practical examples from simple to complex logic
depth. This will enable the reader to have better understanding about how to code
an efficient RTL using Verilog. The synthesizable designs, and frequent issues in
theRTLdesignlifecycleareorganizedineachsectionforthebetterunderstanding.
This book is targeted to the engineering students, inexperienced engineers, and
professionals those who want to implement practical, synthesizable, efficient RTL
using Verilog!
Acknowledgments
Thisbookispossibleduetohelpofmanypeople.Itrulyappreciatetheirdirectand
indirecthelpduringwritingofthisbook.AmongthemIamverymuchthankfulto
my dearest friend, Ishita Thaker (Ish), for encouraging me to write this book. This
book would not have been possible if my wife Somi has not reviewed the book
contents and grammatical mistakes.
Special thanks to my son Siddesh and my daughter Kajal for their ideas and
creative thoughts while creating diagrammatic representation for this book. I truly
appreciate the sacrifices of Siddesh and Kajal.
SpecialthankstoallthestudentstowhomItaughtthesubjectformorethanone
decade.IndirectlyIwanttothankallmyteachersfortheirvaluablehelpduringmy
engineering and postgraduation at IIT Powai (Mumbai).
SpecialthankstoalltheSpringerstaff,especiallySwatiMaherishiandAparajita
Singh for good and encouraging conversations, support, and encouragement.
Special thanks in advance to all those readers across the world for buying,
reading, and enjoying the book!
xi
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Evolution of Logic Design . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 System and Logic Design Abstractions. . . . . . . . . . . . . . . . . 3
1.3 Integrated Circuit Design and Methodologies. . . . . . . . . . . . . 4
1.3.1 RTL Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.3.2 Functional Verification . . . . . . . . . . . . . . . . . . . . . 5
1.3.3 Synthesis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.3.4 Physical Design . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.4 Verilog HDL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.5 Verilog Design Description . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.5.1 Structural Design . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.5.2 Behavior Design. . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.5.3 Synthesizable RTL Design. . . . . . . . . . . . . . . . . . . 10
1.6 Key Verilog Terminologies . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.6.1 Verilog Arithmetic Operators. . . . . . . . . . . . . . . . . 11
1.6.2 Verilog Logical Operators . . . . . . . . . . . . . . . . . . . 11
1.6.3 Verilog Equality and Inequality Operators . . . . . . . . 11
1.6.4 Verilog Sign Operators . . . . . . . . . . . . . . . . . . . . . 13
1.6.5 Verilog Bitwise Operators . . . . . . . . . . . . . . . . . . . 16
1.6.6 Verilog Relational Operators . . . . . . . . . . . . . . . . . 18
1.6.7 Verilog Concatenation and Replication
Operators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.6.8 Verilog Reduction Operators . . . . . . . . . . . . . . . . . 19
1.6.9 Verilog Shift Operators. . . . . . . . . . . . . . . . . . . . . 20
1.7 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2 Combinational Logic Design (Part I). . . . . . . . . . . . . . . . . . . . . . . 27
2.1 Introduction to Combinational Logic. . . . . . . . . . . . . . . . . . . 27
2.2 Logic Gates and Synthesizable RTL. . . . . . . . . . . . . . . . . . . 28
2.2.1 NOT or Invert Logic. . . . . . . . . . . . . . . . . . . . . . . 28
2.2.2 Two-Input OR Logic. . . . . . . . . . . . . . . . . . . . . . . 28
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