Digital Design and Verilog HDL Fundamentals

1166 Pages·2008·10.07 MB·English

by  Cavanagh, Joseph J. F

Digital
Design

Verilog
HDL

and

Fundamentals

74156_FM.indd 1
5/12/08 11:18:53 AM

CRC Press is an imprint of the
Taylor & Francis Group, an informa business

Boca Raton London New York

Joseph Cavanagh
Santa Clara University
California, USA

Digital
Design

Verilog
HDL

and

Fundamentals

74156_FM.indd 3
5/12/08 11:18:54 AM

CRC Press
Taylor & Francis Group
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Boca Raton, FL 33487-2742

© 2008 by Taylor and Francis Group, LLC
CRC Press is an imprint of Taylor & Francis Group, an Informa business

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International Standard Book Number: 978-1-4200-7415-4 (Hardback)

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Library of Congress Cataloging‑in‑Publication Data

Cavanagh, Joseph J. F.
Digital design and Verilog HDL fundamentals / Joseph Cavanagh.
p. cm.
Includes bibliographical references and index.
ISBN 978-1-4200-7415-4 (hardback : alk. paper) 1. Logic circuits--Computer-aided design. 2. Verilog
(Computer hardware description language) 3. Digital electronics. I. Title.

TK7868.D5C3945 2008
621.39’5--dc22
2008012851

Visit the Taylor & Francis Web site at
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By the same author:

DIGITAL COMPUTER ARITHMETIC: Design and Implementation

SEQUENTIAL LOGIC: Analysis and Synthesis

VERILOG HDL: Digital Design and Modeling

________________________

The Computer Conspiracy — A novel

To my son, Brad, for his continued help and support.

PREFACE

The field of digital logic consists primarily of the analysis and synthesis of combina-
tional logic circuits and sequential logic circuits, also referred to as finite-state
machines. The principal characteristic of combinational logic is that the outputs are
a function of the present inputs only, whereas the outputs of sequential logic are a
function of the input sequence; that is, the input history. Sequential logic, therefore,
requires storage elements which indicate the present state of the machine relative to a
unique sequence of inputs.
Sequential logic is partitioned into synchronous and asynchronous sequential
machines. Synchronous sequential machines are controlled by a system clock which
provides the triggering mechanism to cause state changes. Asynchronous sequential
machines have no clocking mechanism — the machines change state upon the appli-
cation of input signals. The input signals provide the means to enable the sequential
machines to proceed through a prescribed sequence of states.
The purpose of this book is to provide a thorough exposition of the analysis and
synthesis of combinational and sequential logic circuits, where sequential logic con-
sists of synchronous and asynchronous sequential machines. Emphasis is placed on
structured and rigorous design principles that can be applied to practical applica-
tions. Each step of the analysis and synthesis procedures is clearly delineated. Each
method that is presented is expounded in sufficient detail with several accompanying
examples.
The Verilog hardware description language (HDL) is used extensively through-
out the book for both combinational and sequential logic design. Verilog HDL is an
Institute of Electrical and Electronics Engineers (IEEE) standard: 1364-1995. The
book concentrates on combinational and sequential logic design with emphasis on
the detailed design of various Verilog HDL projects. The examples are designed first
using traditional design techniques, then implemented using Verilog HDL. This
allows the reader to correlate and compare the two design methodologies.
The book is intended to be tutorial, and as such, is comprehensive and self con-
tained. All designs are carried through to completion — nothing is left unfinished or
partially designed. Each chapter includes numerous problems of varying complexity
to be designed by the reader, including both traditional logic design techniques and
Verilog HDL design techniques in appropriate chapters. The Verilog HDL designs
include the design module, the test bench module which tests the design for correct
functionality, the outputs obtained from the test bench, and the waveforms obtained
from the test bench.
Chapter 1 covers the number systems of different radices such as binary, octal,
decimal, and hexadecimal, including conversion between radices. The chapter also

presents the number representations of sign magnitude, diminished-radix comple-
ment, and radix complement. Binary weighted and nonweighted codes are covered,
including conversion to and from binary-coded decimal (BCD), plus the Gray code.
Chapter 1 also introduces error detection and correction codes that are presented in
more detail in a later chapter.
Chapter 2 presents Boolean algebra and illustrates methods to minimize switch-
ing functions. These methods include algebraic minimization, Karnaugh maps, Kar-
naugh maps using map-entered variables, the Quine-McCluskey algorithm, and the
Petrick algorithm.
Chapter 3 presents the analysis and synthesis (design) of combinational logic cir-
cuits. Examples include sum-of-products and product-of-sums notation, disjunctive
normal forms, and conjunctive normal forms. Logic macro functions are also cov-
ered, including multiplexers, decoders, encoders, and comparators.
Chapter 4 introduces Verilog HDL, which will be used in this chapter to design
combinational logic. Verilog HDL is the state-of-the-art method for designing digital
and computer systems and is ideally suited to describe both combinational and sequen-
tial logic. Verilog provides a clear relationship between the language syntax and the
physical hardware. The Verilog simulator used in this book is easy to learn and use,
yet powerful enough for any application. It is a logic simulator — called SILOS — de-
veloped by Silvaco International for use in the design and verification of digital sys-
tems. The SILOS simulation environment is a method to quickly prototype and debug
any logic function. It is an intuitive environment that displays every variable and port
from a module to a logic gate. SILOS allows single stepping through the Verilog
source code, as well as drag-and-drop ability from the source code to a data analyzer
for waveform generation and analysis. This chapter introduces the reader to the dif-
ferent modeling techniques, including built-in primitives for logic primitive gates and
user-defined primitives for larger logic functions. The three main modeling methods
of dataflow modeling, behavioral modeling, and structural modeling are introduced.
Chapter 5 presents a detailed exposition on the design of computer arithmetic cir-
cuits and includes topics in the following categories: fixed-point addition including
ripple-carry and carry lookahead; fixed-point subtraction; fixed-point multiplication,
including the sequential add-shift technique, the Booth algorithm, bit-pair recoding,
and a high-speed array multiplier; decimal addition and subtraction; decimal multipli-
cation and division; floating-point addition, subtraction, multiplication, and division.
Chapter 6 covers the Verilog HDL design of a variety of computer arithmetic cir-
cuits for fixed-point addition, subtraction, and multiplication and for decimal addition
and subtraction. Fixed-point addition includes implementations of a high-speed full
adder, a 4-bit ripple adder, and a carry lookahead adder. Fixed-point subtraction in-
cludes a unit that combines addition and subtraction. Fixed-point multiplication in-
cludes the implementation of a Booth algorithm circuit for signed operands in 2s
complement representation and a high-speed array multiplier. Decimal addition and
subtraction circuits are also designed, including a 9s complementer for subtraction.
Chapter 7 presents methods of analysis and synthesis for synchronous and asyn-
chronous sequential machines. These techniques form the basic mechanisms for ef-
fective analysis and synthesis. Each method of analysis is accompanied by
appropriate examples. The synthesis of synchronous sequential machines includes

methods to design registers, counters, Moore machines, and Mealy machines. The
synthesis procedure is outlined, then methods are described to determine state equiv-
alence. If equivalent states can be identified, then redundant states can be elimi-
nated, resulting in a machine with a minimal number of logic gates. The primary
focus of this chapter is on the synthesis of deterministic synchronous sequential ma-
chines in which the next state is uniquely determined by the present state and the
present inputs. This chapter also covers the analysis and synthesis of asynchronous
sequential machines where state changes occur on the application of the input signals
only — there is no machine clock. A final topic is the analysis and synthesis of
pulse-mode asynchronous sequential machines in which each input variable is active
in the form of a pulse. There is also no clock input in pulse-mode asynchronous se-
quential machines.
Chapter 8 applies the concepts given in Chapter 7 to design methodologies using
Verilog HDL. Synchronous Moore and Mealy machines are designed using tradi-
tional methods and then implemented in Verilog HDL using various modeling con-
structs. A synchronous counter is designed that counts in a nonsequential pattern.
Various asynchronous sequential machines are designed using dataflow modeling,
behavioral modeling, structural modeling, and mixed design modeling, which incor-
porates two of the previous modeling constructs. Moore and Mealy pulse-mode
asynchronous sequential machines are designed using different Verilog HDL model-
ing constructs.
Chapter 9 presents topics in programmable logic and discusses their use in both
combinational and sequential logic circuits. The programmable devices include a
programmable read-only memory (PROM), a programmable array logic (PAL), a
programmable logic array (PLA), and a field-programmable gate array (FPGA).
Chapter 10 covers topics in digital-to-analog (D/A) conversion and analog-to-
digital (A/D) conversion. Operational amplifiers are introduced, which are integral
devices used in converting from digital to analog and from analog to digital. The
digital-to-analog methods include a binary-weighted resistor network D/A converter
and an R – 2R resistor network DA converter. A special type of operational amplifier
called a comparator is introduced, which is used in analog-to-digital conversion. The
analog-to-digital methods include a counter A/D converter, a successive approxima-
tion A/D converter, and a high-speed simultaneous (of flash) A/D converter.
Chapter 11 presents magnetic recording fundamentals, which covers different
techniques to encode digital data on a magnetic recording surface. The encoding
concepts are applicable to disk drives, tape drives, and other magnetic systems. The
following encoding methods are introduced: return to zero, nonreturn to zero, nonre-
turn to zero inverted, frequency modulation, phase encoding, modified frequency
modulation, run-length limited, and group-coded recording. Peak shift and write
precompensation are also covered plus a section on vertical recording.
Chapter 12 presents additional topics in digital design. Functional decomposi-
tion is a process of decomposing a function into smaller functions for the purpose of
minimization; that is, to hierarchically decompose a system into its functional com-
ponents. Functional decomposition examples are designed using traditional methods
and then implemented using Verilog HDL. Iterative networks are one-dimensional or
multi-dimensional arrays of identical cells in which the output of a cell depends on

the input from previous cells. Typical applications are sequence detectors, shift reg-
isters, and array multipliers. Examples of iterative networks are designed using Ver-
ilog HDL. The section on Hamming code error detection and correction expands the
concepts presented in Chapter 1 by providing the theory, logic design, and Verilog
design of a Hamming code circuit. An overview of the cyclic redundancy check
(CRC) code is presented. Residue checking and parity prediction techniques are dis-
cussed relative to detecting errors in arithmetic operations. An arithmetic and logic
unit (ALU) is designed using Verilog HDL and a section on memories is discussed
and a typical memory is designed using Verilog HDL.
Appendix A presents a brief discussion on event handling using the event queue.
Operations that occur in a Verilog module are typically handled by an event queue.
Appendix B presents a procedure to implement a Verilog project. Appendix C con-
tains the solutions to select problems in each chapter.
The material presented in this book represents more than two decades of com-
puter equipment design by the author. The book is intended as a text for a two-
course sequence on combinational and sequential logic design. Chapter 1 through
Chapter 6 can be used for combinational logic; Chapter 7 through Chapter 12 can be
used for sequential logic. The book presents Verilog HDL with numerous design
examples to help the reader thoroughly understand this popular hardware description
language.
This book is designed for undergraduate students in electrical engineering, com-
puter engineering, and computer science, for graduate students who require a non-
credit course in logic design, and for practicing electrical engineers, computer
engineers, and computer scientists.
A special thanks to Dr. Ivan Pesic, CEO of Silvaco International, for allowing
use of the SILOS Simulation Environment software for the examples in this book.
SILOS is an intuitive, easy-to-use, yet powerful Verilog HDL simulator for logic ver-
ification.
I would like to express my appreciation and thanks to the following people who
gave generously of their time and expertise to review the manuscript and submit
comments: Professor Daniel W. Lewis, Chair, Department of Computer Engineering,
Santa Clara University, who continues to support me in all my endeavors; Dr. Geri
Lamble; Steve Midford for his helpful suggestions and comments; and Ron Lewer-
enz. Thanks also to Nora Konopka and the staff at Taylor & Francis for their sup-
port.

Joseph Cavanagh

CONTENTS

Chapter 1
Number Systems, Number Representations,
and Codes 1

1.1
Number Systems 1
1.1.1
Binary Number System 4
1.1.2
Octal Number System 7
1.1.3
Decimal Number System 9
1.1.4
Hexadecimal Number System 10
1.1.5
Arithmetic Operations 12
1.1.6
Conversion Between Radices 22
1.2
Number Representations 29
1.2.1
Sign Magnitude 29
1.2.2
Diminished-Radix Complement 31
1.2.3
Radix Complement 34
1.2.4
Arithmetic Operations 38
1.3
Binary Codes 59
1.3.1
Binary Weighted and Nonweighted Codes 59
1.3.2
Binary-to-BCD Conversion 63
1.3.3
BCD-to-Binary Conversion 64
1.3.4
Gray Code 65
1.4
Error Detection and Correction Codes 68
1.4.1
Parity 68
1.4.2
Hamming Code 70
1.4.3
Cyclic Redundancy Check Code 72
1.4.4
Checksum 73
1.4.5
Two-Out-Of-Five Code 75
1.4.6
Horizontal and Vertical Parity Check 75
1.5
Serial Data Transmission 77
1.6
Problems 78

Chapter 2
Minimization of Switching Functions 83

2.1
Boolean Algebra 83
2.2
Algebraic Minimization 92
2.3
Karnaugh Maps 95
2.3.1
Map-Entered Variables 113
2.4
Quine-McCluskey Algorithm 118
2.4.1
Petrick Algorithm 123
2.5
Problems 128

Chapter 3
Combinational Logic 137

3.1
Logic Primitive Gates 138
3.1.1
Wired-AND and Wired-OR Operations 148
3.1.2
Three-State Logic 150
3.1.3
Functionally Complete Gates 150
3.2
Logic Macro Functions 154
3.2.1
Multiplexers 155
3.2.2
Decoders 173
3.2.3
Encoders 185
3.2.4
Comparators 189
3.3
Analysis of Combinational Logic 194
3.4
Synthesis of Combinational Logic 205
3.5
Problems 223

Chapter 4
Combinational Logic Design
Using Verilog HDL 231

4.1
Built-In Primitives 232
4.2
User-Defined Primitives 267
4.2.1
Defining a User-Defined Primitive 267
4.2.2
Combinational User-Defined Primitives 267
4.3
Dataflow Modeling 289
4.3.1
Continuous Assignment 289
4.3.2
Reduction Operators 312
4.3.3
Conditional Operator 315
4.3.4
Relational Operators 318
4.3.5
Logical Operators 320
4.3.6
Bitwise Operators 322
4.3.7
Shift Operators 326
4.4
Behavioral Modeling 328
4.4.1
Initial Statement 329
4.4.2
Always Statement 332
4.4.3
Intrastatement Delay 339
4.4.4
Interstatement Delay 341
4.4.5
Blocking Assignments 343
4.4.6
Nonblocking Assignments 345
4.4.7
Conditional Statement 351
4.4.8
Case Statement 356
4.4.9
Loop Statements 365
4.4.10 Tasks 370
4.4.11 Functions 374
4.5
Structural Modeling 378
4.5.1
Module Instantiation 378
4.5.2
Ports 379