Digital design

599 Pages·2007·177.849 MB·English

by  M Morris Mano, Michael D Ciletti

Digital Design
M. Morris Mano
Emeritus Profemr of Computer Engineering
Callfornio Stote University, Los Angeles
Michael D. Ciletti
Department of Wricol and Conputor Engineering
University of Colomdo at Cd~adOSp rings
L4PEARSON
Upper Saddle River, Nl07458
Contents
Preface ix
1 Digital Systems and Binary Numbers 1
1.1 Digital Systems
1.2 Blnan Numbers
1.3 b umber-Bare Conversions
1.4 Octal and Hexadecimal Numben
1.5 Complement9
1.6 Signid Binary Numbers
1.7 Binary Coder
1.8 Binary Storage and Registers
1.9 Binary Logic
2 Boolean Algebra and Logic Gates 36
2.1 Introduction
2.2 Basic Definition! .
2.3 Axiomatic Definlhon of Boolean Algebra
2.4 Basic Theorems and Pmpemier
of Boolean Algebra
2.5 Boolean Functions
2.6 Canonical and Standard Farms
2.7 Other Logic Operations
2.8 Digital Logic Gates
2.9 Integrated Circuit9
3 Gate-Level Minimization 70
3.1 intmductio~l 70
3.2 The Map Method 70
3.3 Four-Variable Map 76
3.4 FNeYariable Map 81
3.5 Pmduct-of-Sums SlmpliRcation 83
3.6 Don't-Care Conditions 86
3.7 NAND and NOR implementation 89
3.8 Other Twplwel ImplementaUonr 96
3.9 DLcIus~V~OFRu nction 101
3.10 Hardware Descriwon Language 106
4 Combinational Logic 722
4.1 Introduction 122
4.2 Combinational Circuit3 122
4.3 Analyds Pmcedure 123
4.4 Design Pmcedure 126
4.5 BinaryAdder-Subtractor 130
4.6 Decimal Adder 139
4.7 Bhary Multiplier 142
4.8 Magnitude Comparator 144
4.9 Decoden 146
4.10 Encoders 150
4.1 1 Multiplexen 152
4.12 HDL Models of Combinational Circuits 159
5 Synchronous Sequential Logic 182
5.1 lnvodunion 182
5.2 Sequential Circuits 182
5.3 Storage ElemenD: Latches 184
5.4 Storage Uemenk: FlipFiops 188
5- .5- Analvrir of Clocked SeawnUal Circuits 195
5.6 ~~n&erirablHeD L M&S of Sequential
Circuits
5.7 State Redudon and Aulgnment
5.8 Design Pmcedure
6 Registers and Counters 242
6.1 Registers 242
6.2 Shift Registen 245
6.3 Ripple Counten 253
6.4 Synchmnous Counters 258
6.5 Other Counten 265
6.6 HDL for Registen and Counters 269
7 Mernorv and Proararnrnable Loaic 284
intmduction
Random-Access Memory
Memory Decoding
Error Detection and Correction
Read.Oniv Memow
Prcgrammanle Logic Array
Programmaole Array Logic
Sequentai Programmable Devices
8 Deslgn at the Rcglster
Transfer Level 334
8.1 intrcduction
8.2 Register Transfer Lwei (Rn) Notation
8.3 Register Transfer Lwei in HDL
8.4 Algorithmic State Machines (ASMs)
8.5 Design Example
8.6 HDL Dexription of Design Example
8.7 Sequential Binary Multiplier
8.8 Control Logic
8.9 HDL Description of Binary Multiplier
8.10 Design with Multiplexen
8.11 Race-Free Design
8.12 Latch-Free Design
8.13 Other Language Featum
9 Asvnchronous Seauentlal Leaic 415
introdunion
Analysis Pmedun
Circuits with Latches
Design Procedure
Reduction of State and Flow Tables
Race-Free State Assignment
Hazards
Design Example
vl Contents
10 Digital Integrated Clrcuits 471
10.1 introduCfion
10.2 Special Characteristicr
10.3 Bipolar-TransistorC har~terirticr
10.4 Rnand DTLCircuits
1.5 Transistor-Transistor Logic
10.6 Emitter-Coupled Logic
10.7 Metal-Oxide Semiconductor
10.8 Complementary MOS
10.9 CMOS Transmission Gate Circuits
10.10 Switch-Lwel Modeling wiVl HDL
11 Laboratory Experiments
with Standard ICs and FPGAs 51 1
11.1 Introduction to Experiments
11.2 Experiment 1: Binary and Decimal Numbers
11.3 Experiment 2: Digital Logic Gats
11.4 Experiment 3: Simplification of Boolean
Functions
115 Experiment4: Combinational Circuits
11.6 Experiment 5: Code Converters
11.7 Experiment 6: Design with Multiplexers
11.8 Experiment 7: Addersand Subtractors
11.9 Experiment 8: FiipFiopr
11.10 Experiment 9: Sequentiai Circuits
11.11 Experiment 10: Counters
11.12 Experiment 11: Shift Registers
11.13 Experiment 12: Serial Addition
11.14 Experiment 13: Memory Unit
11.15 Experiment 14: Lam Handball
11.16 Experiment IS: ~iocf-~ulsGee nerator
11.17 Ex~erimen1t 6: Parallel Adder and
~icumulator
11.18 Experiment 17: Binary Multiplier
11.19 Exlleriment 18: I\rynchmnous Sequential
Cikuits
11.20 Verilog HDLSimulation Experiments
and Rapid Prototyping with FPGh
12 Standard Graphic Symbols 559
12.1 Rexang~Ia-SnapeS ymbols
12.2 Qualnynng Symwls
12.3 Dependency (uota~on
12.4 Symbols for Combinational Elemen6
12.5 Symbols for Flip-Flops
12.6 Symbols for Registers
12.7 Symbols for Counten
12.8 Symbol for RAM
Answers to Selected Problems
Index
Preface
L ) l p l s l c ~ ~ ~ 1 ~ 1 n ~ ~ d F C I I p ~ . ~ p l s y a . ~ u l s m a r r r n m -
puma, bu xnm &d rplW &wear. OPS &splsyr PDd mmy mkr m - pod-
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a bebvidm odel of the circuit's f m c d o ~a,nd lhcn nym&iziq thnt dcseription inm
a hardware realiitioo 111 % pudd.r tshnology, c.g... CMOS intcgmd Eirsuia or field-
pgmmmblcgare unya (FRl48). No longor s wvelw, Y, &+Itm k me noar rrrdily
~Wblmc mini~aitia~n.d src m i w ein a -pic wnv fmm mduue kvcl nuricula
M &ink, as odhmpl.h dbr&. PDd logic d y ml ~w epV~idll of
.c- u, Ibb histion of & mu addr ama niglt lo& ussofimdwnd ucriplioo Inn-
in dCLi~&~rca~l~ luts~
hadwan w*. 'Phlu, an main s k.m@ mml dsomthuid sod qusnri.l logic
&vices. hmdh ip pmxim uc pcumsd and W!d m&re -pad rim those ob-
oind vnh a HDL-based @gm. mu ve am pmrntins. hovevu. is a shiR 111 emphaair
on how hniwam u &signcd, a sshiftthat, we Umk, bener pqm.? s stodmt far a c- m
today's industry, where HDL-kd d4gn p t i ma te prsvalmt.
FLEX1,BILITY
The wqueme of topics in the tea can aecommodatcmvrses thatadbne to uaditiooal, manu-
al-bed,aatmmuafdigital~gn.comsthat~dcsignusioganHDanLd,c o-that
m in hansition beween or blendthe two sppmachcs. Because mob synthesis tmls at+
matidy paform logic minimhion, Kamaugh maps and rrLslrd topics in oplimirarioncan
kpnnentcdat~beginniogoafu eatmmt ofdigitaldesign, orthey canbe-otedaftecci-
airs and their applicaions areexmind, designed. and simulatedwith anHDL. The win-
d hbo th manual and HDL-bwd dcsigo uampln. Our md-ofchapta pnobicmr funher
faelhtau~ns cxihhly b) ms-refcmmgproblems tha addrrssa mdeoda ld desw
task a tth acornparum pro.b. le m that uwr an HDL-ta aecompluh the I& Ad~Po~wye ,Id
imn aannuari uanadl oH &DreLd-~ b l~e~dp~ raobnlnemosa~ ~u~r tk~h b~e v, e mPn ~d a ~oe~fn~ tahne *n m*.-n aanlde idn riehen ru~o~l~l eu~d ti~o~~nm rmulasotulaoln. t~r o the err
WHAT'S NEW?
Tbc previous edition of Ulis Wtm agni2ed the impartMoe ofhard- dcsedptioo langoages
io the design of digitalcincuiu, and incmpRtednew matuial mduampkr intmducing rm-
~totheWoglaoguagDasdefiocdby~Sfandardl364-1~5.~reviionupdatss
and expaads that mamen1 by:
- misiH~D L-based empln1 0 presentthe ANS1.C like SynW that was adopted in the
stm& IEEE 1364-2001 aodIEa 13W2005
enr~tbatsllHDLuampicndmto~-aEnpcdpraetiecsformWgdig-
.
ital cima
.
proyiding a ~yswmticm uhodology for deigning a datapslb eonmlla
-ting sclcnedcxercires and aolvtims m md-ofcbsptcr problems in Verilog IS95
.
and Verilog ZWlW5 synm
- introducing an imponant design taal -the algorithmic sratc machine and datapath
(ASMD) EbM
wising the end-ofshaptv pblem and urnding the s to f pbkrm by including
ovu 75 additional problems
pviding swdenu with fully developed mwcrs m selcnedpmblems, including simu-
-
Istion mule
providing smdena with a CD-ROMc ontaining simulator-dy HDL aolutionr of an-
.
S Wto ~selw tedpmbkm
upanding the lteament of pmpmmbk logic devices to indude FPOAs
.
revising the sclutions manval and web-band materials and msudng that &lions d
HDL-based exercises wnfmm lo indumy praE6-l for modelling with an HDL
bsainga nd demonsm@ Ihe impmncco f lcst plaoa for vrrifying HDL models of
EireviD
- pmviding iwtrucm with vedficd simuhlopready soume code ad ndr hbe.chcs for all
omd.of ch.pmproblcm
maki"8.U figares, mbb, and HDLsrmples available to i m mfor downloading
in PDF formar fmm the publisha
inelu~withhebcoka~.ROMwith~alsadsimulnorsforhe~lP95and
EEB-2OOl SIawhds dthcVerilo8lsnguagc
In addi6-m m th above Mbanscmcou, the m ti ncmponfcs more m h i dm aterial m bee
tcr rene lumaw ho sle micnted Wsrd agraphid d u r nA nnowedgraphical ~rultasd
aplmtio~oif ~ ~are prrsrcnld to henlp snulco u undmtsnd digid cirmis and lo fa-
nliufc c1l~ssm.md ismsdmu olthcm. -ugh map. me pnxmd with additid graphics.
DESIGN METHODOLOGY
dtiono f thc lea exen& thpmioud editiw's m m n to f &ou6 hnifc mtem a-
s hby p ucnua a sysQmaoc memodology fadeqmga mfc marhmne mmnml hedata-
@of ad~gidry rwrn Mmva.t he hewmkl a uhrh thlr malmal ,s pmmled -Ihr
rraluoc unuum rn wkht hc mmUm YVI 61W horn Ih dmmIh e thc %v$mmha s fed-
ba~k% methc-~ogyisq pliceie to ma.& and ~~~rtmed&rsxchteos' bzgn
HDL-bASED APPROACH
It is not ruffic~foar. inhodunion lo HDLs to dwell on ian@agc syorar. We present only
thMc elements dthc Veriloe lanewe that am marched to the level and rsooe of Ws ten.
Abo. -1 syntax dasn oLgun&& that a model mssrs a flmetiod specik~cationo r that
it can h synthctivd inlo phystcal hardware We inrmduse students to .dlxtpbncd use of
ioduswbaaedpctim for moogmadcls locnrwe Ihal ahha\ioral dnolptioo can hsyo-
thesued ,nu, ~hv%nbla rdwsrr. and thsr Ue hhavnn d the aolhewcd ckuit will mash
diti- in he HDL madelsbf wrh m01:k. mec onditi&r in the tcstbeoeh used lo verify
Ihem. md n rnmrmatch hwmt he terults of srmulaoq a hchsvid model and 1% rynlhe
wcdphyredmvrpur Slrmlmly,fmkurm.hdcby (nduslripmakesmay ludtodwps
ths s~mulslee medv. hm whtheh have bard- lsrchcr tha~M lnrmduccd mm he &sum
aetidcnWy sa a e&!se~ &he modelling rwlcuscd by he higno. inmulw-b&d
msrnodology wcpcv.r I& m -.Gee and I&-Geeduiglrr 11 iimi -1 hat afvdmts
leam and foUw indusoy -cn u dogH DL models. indepndcnt of luhclma smtudcnt'r
cmkulum has mulo synthuir tarlr.
xli Prehce
VERIFICATION
h~,si~teffeatisup~wv~WIhe~~naliityofa~uitiscomnYu
nnmuchatmrionis nivmtovaific~onininMduclory~~~digi81~Swighnc,r cIheh
is on design irxlf, ond =dog is viewed as a secondary uodarling. Our is
that this view can lead to pemme declmtim that "thc Ehnrit works beauWy? Likewise.
indusqgsinsrepeated~o11i~~inv~tmenfinonHDLmod~e~1ubdyn gtbatiIUmdabIc,
mmbleandr~usablPW. e 6 $ r m % u a s d b andIhehsu&of~-. Wealno~m
;idc sst benches for all of the solutions and s -& to (1) vedfy tb; function& of Gdr-
cuih (2) uodsnsore the importanceof thnough mting, and (3) hmduce sludcar toimpMan1
mnssptb. ~urha, 3dfshccl;mg tea bcnchc5 Advmaung and ~ U ~ s imhc dgrv clopmcnt nf s
rerrplan u, gut& the hcdsvslopmuu of a test bcmb. ac m b s cI km m me Wil and a@
ihcm in the wluuvnr manual and m thc hcwmu , r c l dp mbl-a Ik ado f lbs ic*
HDL CONTENT
This ediho f the text ~pdatesa nd expands its tl~armsnot f the Vnilog Hard- Dsscrip
tion Laogoage @DL) and exploits key eobanccmem available in IEEE Standards 13M2M1
and 13643005. Wehahave a r dm ar all-pla in the tura nd all msmi n the salutiao
manual conform to accented indvsuv d ~ cfor8 mo delioe diaital hardardarr As in the or-
Yiow edition, HDL m&al in inr&d in inwpas aectim;so;t con be covered or skip&
a. &iced. docs not diminish treatment of manual-based design, and does nndiEtas Ihe ss-
quence of p-ntatioo. Tbe aaatment in ar a level suitable for beginoing stude0ts fa are
icamiog di#tal circuib and a hardware d~w;nptionla nguage at Ihe same lime. The mtpn
pans nudents to work on significant iodepeodent design pmjccts md to sued in 1 later
COW.S COIOpUW~hi~.
Digital circuit 8$,, a intmduced iD Chapthapt 1 lhmugh 3 with an inmduction U, vaiiog
.H DLin Sedon3.10.
fuaba discussion of mAelh8 with HDLs murs io Section 4.12 foUod the sMy
ofsombin81id circuits.
sequential ch~itasr c covdi n Chapm 5 and 6 with cornpondin8 HDL aamph
.i n Sectione 5.6 and6.6.
.T hcHDLdesdption of memory is prercntedio Section 72.
.T hcRnsymbols usedin Vwilog arc inaucedin Sections 8.3.
Examples af RTLandsrmctmJmodelr invedlog are pmvidedin Seetiona 8.6 and 8.9.
Chapter 8 also-1s a new. somprehennivc hwtmcnt of HDLbased design of a data-
path rnnmUET.
Won1 0.10 cover8 switch-lcvclmadeling ~onn@gto CMOS c-U.
Sdon l1.20 suppimtst hc hard- upwimenb ofchapfer 11 with HDL urpcd-
men*. Now me cimits designed in U l econ b~e cbsr~cd by modeling &em lo
v&gondaim~g~beha~or.Thcn~~aobesynh~and~~edwith
on PPOAO" a pmtoryping baa.