Digital CMOS Circuit Design

366 Pages·1986·31.681 MB·English

by  Marco Annaratone (auth.)

DIGITAL CMOS CIRCUIT DESIGN
THE KLUWER INTERNATIONAL SERIES
IN ENGINEERING AND COMPUTER SCIENCE
VLSI, COMPUTER ARCHITECTURE AND
DIGITAL SIGNAL PROCESSING
Consulting Editor
Jonathan Allen
Other books in the series:
Logic Minimization Algorithmsfor VLSI Synthesis. R.K. Brayton,
G.D. Hachtel, C.T. McMullen, and A.L. Sangiovanni-Vincentelli.
ISBN 0-89838-164-9.
Computer-Aided Design and VLSIDevice Development. K.M. Cham,
S.-Y. Oh, D. Chin, and J.L. Moll. ISBN 0-89838-204-1.
Adaptive Filters: Structures, Algorithms, andApplications.
M.L. Honig and D.G. Messerschmitt. ISBN 0-89838-163-0.
Introduction to VLSISilicon Devices: Physics, Technology and
Characterization. B. EI-Kareh and R.J. Bombard.
ISBN 0-89838-210-6.
Latchup in CMOS Technology: The Problem andIts Cure.
R.R. Troutman. ISBN 0-89838-215-7.
DIGITAL CMOS CIRCUIT DESIGN
by
Marco Annaratone
Carnegie-Mellon University
Pittsburgh, Pennsylvania
.,
~
KLUWER ACADEMIC PUBLISHERS
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LibraryofCongressCataloging-in-PublicationData
Annaratone, Marco.
DigitalCMOScircuitdesign.
(The Kluwer internationalseriesinengineeringand
computerscience. VLSI, computerarchitecture, and
digitalsignal processing)
Includesindex.
1. Metaloxidesemiconductors, Complementary.
2. Digitalelectronics. 3. Integratedcircuits
Verylargescaleintegration. I. Title. II. Series.
TK7871.99.M44A56 1986 621.395 86-10646
ISBN-13:978-1-4612-9409-2 e-ISBN-13:978-1-4613-2285-6
001: 10.1007/978-1-4613-2285-6
Copyright © 1986byKluwerAcademicPublishers
Allrightsreserved.Nopartofthispublicationmaybereproduced,storedinaretrievalsystem,
ortransmittedinanyformorbyanymeans, mechanical, photocopying, recording, orother
wise, withoutthepriorwrittenpermissionofthepublisher,KluwerAcademicPublishers, 101
PhilipDrive, Assinippi Park, Norwell, Massachusetts02061.
PrintedintheUnitedStatesofAmerica
To Hanni(and Vanessa, ofcourse)
Contents
Foreword xi
Preface xiii
1. Introduction 1
1.1. FromnMOStoCMOS 3
1.2. CMOSBasicGates 8
2. MOSTransistorCharacteristics 15
2.1. TheMOSTransistor 15
2.2. ParasiticParameters 28
2.3. SmallGeometryMOSTransistor 36
2.4. CMOSTransmissionGate 41
2.5. CMOSInverter 44
2.6. AMoreAccurateModelfortheCMOSInverter 49
2.7. CMOSPowerDissipation 55
3. FabricationProcesses 61
3.1. Thep-wellFabricationProcess 62
3.2. Then-wellFabricationProcess 66
3.3. LOCMOSTechnology 68
3.4. Latchup 71
3.5. TheTwin-tubFabricationProcess 79
3.6. TheSOSFabricationProcess 80
3.7. Bulkvs. SOl 82
3.8. DesignRules 83
4. LogicDesign 89
4.1. StaticLogic 93
4.1.1. ComplementaryLogic 93
4.1.2. nMOS-likeLogic 94
4.1.3. TransmissionGateIntensiveLogic 98
4.1.4. CascodeLogic 100
4.2. DynamicLogic 103
4.2.1. Ripple-through Logic 105
4.2.2. P-ELogic 111
viii DigitalCMOSCircuitDesign
4.2.3. ClockedCMOSLogic 113
4.2.4. DominoLogic 114
4.2.5. NORALogic 117
4.3. ChargeSharing 121
4.4. Bootstrap Logic 124
4.5. LogicDesignattheSystemLevel 128
5. CircuitDesign 133
5.1. Resistance, Capacitance,and Inductance 134
5.1.1. InterconnectResistance 136
5.1.2. InterconnectCapacitance 137
5.1.3. InterconnectInductance 143
5.1.4. InterconnectDiscontinuities 143
5.1.5. CouplingParametersandInterconnectDelay 144
5.1.6. DiffusionResistance 146
5.1.7. Contact Resistance 147
5.2. ModelingLongInterconnects 149
5.3. TheConceptofEquivalentGateLoad 152
5.4. DelayMinimization 155
5.4.1. InverterDelayandSizing 156
5.4.2. InverterChainSizing 159
5.4.3. InverterChainSizingwithStrayCapacitance 162
5.5. TransistorSizinginStaticLogic 163
5.6. TransistorSizinginDynamicLogic 165
6. DesignofBasicCircuits 173
6.1. StorageElements 174
6.2. Full-adder 178
6.3. ProgrammableLogicArray 181
6.4. Random-accessMemory 186
6.4.1. MemoryCell 188
6.4.2. Decoder 191
6.4.3. SenseAmplifier 193
6.5. ParallelAdder 204
6.6. ParallelMultiplier 209
6.6.1. The Design of a Multiplier Based on the
ModifiedBoothAlgorithm 211
6.6.2. BasicBuilding-blocksInsidetheArray 213
6.6.3. TheProblemofSignExtension 216
6.6.3.1. The"SignPropagate"Method 217
6.6.3.2. The "SignGenerate" Method 222
6.6.4. The Implementation of a 24-bit
CMOSBoothMultiplier 226
Contents ix
7. DriverandI/OBufferDesign 233
7.1. CMOSInverterDelayEstimation 234
7.1.1. Fall-timeDelayEstimation 243
7.1.1.1. Region 1: n-channel Device in
Saturation 244
7.1.1.2. Region 2: n-channel Device in
LinearRegion 248
7.1.2. Rise-timeDelayEstimation 252
7.1.3. RefiningtheModel 252
7.2. InputBuffer 257
7.3. OutputBuffer 261
7.4. Tri-stateOutputBufferand I/OBuffer 272
7.5. OutputBufferandBusDriverDesignOptimization 274
7.5.1. UnconstrainedDelayMinimization 275
7.5.2. ConstrainedDelayMinimization 282
7.6. InputProtection 287
7.7. OutputProtection 294
7.8. DrivingLargeOn-chipLoads 295
AppendixA. Layout 301
A.I. GeneralConsiderationsonLayout 302
A.2. Layout Methodologies for Latchup Avoidance 310
A.3. LayoutwithStructuredMethodologies 313
A.4. PowerandGroundRouting 315
AppendixB.InterconnectCapacitanceComputation 319
B.I. Case 1: CoupledMicrostripStructure 320
B.2. Case2: CoupledStriplineStructure 321
AppendixC. FiguresfromSection5.4.2 323
AppendixD.DelayMinimizationBasedonEq. (7·3) 327
AppendixE.EquationsRelatedtoFig.7·10 337
AppendixF. SymbolsandPhysicalConstants 339
Index 341
Foreword
In light of decreasing feature size and greater sophistication of modern
processing technology, CMOS has become increasingly attractive, pro
viding low-power (at moderate frequencies), good scalability, and rail-to
rail operation. For many designers, particularly those approaching VLSI
from a system viewpoint, previous experiencehas beenmainly with ratioed
NMOSdesign, andsothereisaneedto buildonthisexperienceandmakea
naturaltransitionintoCMOSdesign. Indeed, thereismuchthatcanbebor
rowed from NMOS experience, mainly centered around the techniques for
creating N channel pulldown structures. Based on these contributions,
CMOS has now grown to the point where there are several circuit styles
which haveevolved, and theseareamplydescribed inthisbook. Startingat
the level oftheindividualMOSFET, basicbuildingblocksaredescribed, as
well as the variety ofCMOS fabrication processes in contemporary usage.
Circuitstyleissuesarethenexpandedto providetheuserwithseveraluseful
designmethodologies, andmuchcareisgiventoelectricalperformancecon
siderations, including characteristics of interconnect, gate delay, and I/O
buffering. This understanding is then applied to macro-sized components,
including array multipliers, where the reader acquires a unified view ofar
chitectural performance through parallelism, and circuit performance
throughscrupulousattentiontodevicesizingandcontrolofparasiticcircuit
elements. In addition, layout techniques to avoid latchup, a consideration
not previously encountered by NMOS designers, are given careful
treatment.
DesignerswhoareapproachingCMOSfrom previous NMOSexperience,
orthosewhoarecontemplatingtheir first designs, will find arichtreatment
ofmajordesignissuescenteredaroundCMOS, inastylethatisthoughtful,
detailed, and broad from the system perspective. The emerging high
performance designs will partake of the benefits of increasingly exciting
process and circuit innovation, forming the basis for lasting contributions
to contemporary digital design.
Jonathan Allen
Consulting Editor
Preface
Complementary metal-oxide semiconductor (CMOS) technology has become the
most effective fabrication process for the production of very large-scale integrated
(VLSI) digital circuits. Moreover, there is wide-spread consensus that no other
technology will effectively compete with CMOS for many years to come. It is
therefore essential for the VLSI circuit designer to fully master the wide range of
possibilitiesthatCMOScanoffer.
The purpose ofthis book is not simply to present and discuss the most important
techniquesusedinthedesignofCMOS digitalcircuits. Rather, digitalCMOSdesign
is dealt with in the realm ofconstantly decreasing feature sizes, which poses new
challengesto the designer in search ofultimate speed. Aquick look atthe Tableof
Contents exemplifies this: interconnection and off-chip communication delays are
dealtwithextensivelyinChapters5and7.
As is well-known, the intrinsic gate delay no longer dictates circuit speed.
Interconnection and off-chip communication delays represent far more important
limitations. This is another reason why other technologies featuring shorter gate
delay than CMOS- such as Gallium Arsenide, in particular- will not necessarily
prevail in the shortterm. Smaller feature sizeswill also require lowerpowersupply
voltage. Although it is still possible to use the standard 5V power supply for
micrometer technologies, sub-rilicron processes will necessitate lower voltages. with
dramatic effects on design methodologies. Lower voltages and smaller parasitic
capacitances make dynamic logic design less reliable, noise problems may call for
differential interconnections. and so on. Therefore. it is crucial to realize that the
approachtothedesignofhigh-performancechipsmustbereconsidered.