Digital Algorithms for Linearity Improvement of Current-Steering Digital-to-Analog Converter

134 Pages·2015·5.67 MB·English

Digital Algorithms for Linearity Improvement of
Current-Steering Digital-to-Analog Converter

DISSERTATION
Submitted by

SHAIFUL NIZAM BIN MOHYAR

In partial fulfillment of the requirements for the award of the Degree of

DOCTOR OF PHILOSOPHY
IN
ELECTRONICS & INFORMATICS ENGINEERING

Under the guidance of

PROFESSOR HARUO KOBAYASHI, Ph. D. Eng.

DIVISION OF ELECTRONICS & INFORMATICS
GRADUATE SCHOOL OF SCIENCE & TECHNOLOGY
GUNMA UNIVERSITY
JAPAN

March 2015

Acknowledgement
Acknowledgement
Special thanks to my supervisor Professor Dr. Haruo KOBAYASHI
for his great guidance and support. Without his support this study could
not have been done properly.
I am gratefully acknowledges the research support from members
of Semiconductor Technology Academic Research Center (STARC)
group for their priceless advice and support during my study. My great
appreciation also goes to Dr. Takahiro MIKI from Renesas Elelctronics,
members of our ADC/DAC group (especially Mr. Yutaro KOBAYASHI)
and my colleague, Mr. Shu WU for their valuable discussion time towards
of this work. I would like to thank to Associate Professor Dr. Nobukazu
TAKAI and Mr. Nobuyoshi ISHIKAWA to their valuable support during
my present in Kobayashi laboratory.
I would like to thank my review committee members, Professors, Dr.
Kuniyuki MOTOJIMA, Dr. Sadao ADACHI, Dr. Yasunori KOBORI and
Dr. Yasushi YUMINAKA.
I would like to forward my gratitude to Universiti Malaysia Perlis
(UniMAP) and the Malaysian Government for permission to pursue Ph.D.
i
Acknowledgement

degree and provide the financial support.
Finally, I also would like to thank to my parent Haji Mohyar Haji
Salleh and Hajah Muslimah Haji Sapuan, my mother in law Hajah Che
Chom Haji Ahmad, my beloved wife Siti Hajar Haji Che Haris and my
sons, Muhammad Azrul Aqil, Muhammad Azrul Arif, Muhammad Azrul
Adha and Muhammad Azrul Anas, for their patience, ‘dhua’, cooperation
and endless moral support.

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Declaration
Declaration

I hereby declare that this submission is my own work and that, to
the best of my knowledge and belief, it contains no material previously
published or written by another person, nor material which has been
accepted for the award of any other degree of the university or other
institute of higher learning, except where due acknowledgement has
been made in the text.

Signature:
Name: Shaiful Nizam Bin Mohyar
Student No.: 12820473
Date:

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Table of contents
Table of contents

Acknowledgement i
Declaration iii
Table of contents iv
List of figures vii
List of table x
Abstract xi

Chapter 1
DATA CONVERTERS - 1 -
1.1 Introduction - 1 -
1.2 Motivation - 1 -
1.3 Objectives - 3 -
1.4 Approach - 3 -
1.5 Outline of the thesis - 4 -
References - 4 -

Chapter 2
DIGITAL-TO-ANALOG CONVERTERS - 5 -
2.1 Introduction - 5 -
2.2 DAC specification - 11 -
2.2.1 General specification - 11 -
2.2.2 Static specification - 12 -
2.2.3 Dynamic specification - 15 -
2.3 High speed DAC architectures - 17 -
2.3.1 Binary-weighted current-steering DAC - 18 -
2.3.2 Unary-weighted current-steering DAC - 19 -
2.3.3 Segmented current-steering DAC - 20 -
2.4 Summary - 22 -
References - 23 -

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Table of contents

Chapter 3
LITERATURE REVIEWS:SOURCES OF THE CURRENT SOURCE
MISMATCH AND THEIR CORRECTION TECHNIQUES - 24 -
3.1 Introduction - 24 -
3.2 Types of errors - 25 -
3.3 Mismatch Sources - 26 -
3.3.1 Effects of transistor mismatch - 26 -
3.3.2 Effects of switching behavior - 27 -
3.3.3 Effects of parasitics - 30 -
3.4 Statistical model design - 30 -
3.5 Correction techniques - 33 -
3.5.1 Dynamic element matching (DEM) based switching
schemes - 33 -
3.5.2 Layout based switching schemes - 41 -
3.5.3 Calibration techniques - 46 -
3.5.4 Return-to-Zero (RZ) switching technique - 55 -
3.5.5 Differential Quad Switching (DQS) technique - 57 -
3.6 Summary - 57 -
References - 60 -

Chapter 4
PROPOSED ALGORITHMS AND CALIBRATION TECHNIQUES - 63 -
4.1 Introduction - 63 -
4.2 Proposed calibration technique I: SFDR improvement algorithm for
current-steering DACs - 63 -
4.2.1 Switching-Sequence Post-Adjustment (SSPA) - 67 -
4.2.2 One-Element-Shifting (OES) algorithm - 68 -
4.2.3 Combination of SSPA and OES (Investigated algorithm) - 71 -
4.2.4 Calibration technique - 72 -
4.2.5 Simulation results and discussion - 74 -
4.2.6 Conclusion - 78 -
References - 80 -

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Table of contents

4.3 Proposed calibration technique II: Algorithm to improve current-steering
DAC linearity by digital calibration of selected pairs of current source
cells - 81 -
4.3.1 Half-unary architecture - 82 -
4.3.2 3-stage current source sorting (3S-CS) algorithm - 84 -
4.3.3 Circuits - 88 -
4.3.3.1 Current source design - 88 -
4.3.3.2 Cascoded current source cell - 89 -
4.3.3.3 Folded cascode current source cell - 94 -
4.3.3.4 Digital current measurement circuit based on
ring oscillator - 97 -
4.3.3.5 Calibration technique - 101 -
4.3.3.6 Consideration of re-calibration - 102 -
4.3.3.7 Look-up table in memory based decoder - 103 -
4.3.4 Clock-tree based layout - 104 -
4.3.5 Simulation results and discussions - 105 -
4.3.6 Conclusion - 110 -
References - 111 -

Chapter 5
CONCLUSIONS - 113 -

List of publications - 116 -

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List of figures

List of figures
Figure 1-1 A DAC used in transmitter path. - 3 -

Figure 2-1 DAC as a black box. - 5 -
Figure 2-2 Basic DAC with external reference. - 6 -
Figure 2-3 Bandwidth employed by the different types of DAC. - 7 -
Figure 2-4 Anti-aliasing transition region of differences type of DAC. - 8 -
Figure 2-5 DAC applications in respect of different resolutions
and sampling speeds. - 11 -
Figure 2-6 Illustration of relation between accuracy and precision. - 12 -
Figure 2-7 Definition of INL. - 13 -
Figure 2-8 Monotonic DAC. - 14 -
Figure 2-9 Non-monotonic DAC. - 14 -
Figure 2-10 Illustration of spurious free dynamic range. - 15 -
Figure 2-11 Phenomenon of glitch. - 15 -
Figure 2-12 Glitch mechanism caused by non-ideal switches. - 16 -
Figure 2-13 DAC with open-loop system. - 16 -
Figure 2-14 DAC with closed-loop system. - 17 -
Figure 2-15 “Set and forget” system. - 17 -
Figure 2-16 A 3-bit binary-weighted current-steering DAC. - 19 -
Figure 2-17 A 3-bit unary-weighted current-steering DAC. - 20 -
Figure 2-18 A (M+N)-bit segmented current-steering DAC. - 20 -
Figure 2-19 Normalized required area versus percentage of
segmentation [3]. - 21 -

Figure 3-1 A 3-bit unary weighted DAC with ideal current source cells
and linear tranfer function (dashed blackline). - 28 -
Figure 3-2 Illustration of temperature measurement using a classic
thermometer. - 28 -
Figure 3-3 Non-linear tranfer function (solid red line) caused by
mismatched current source cells. - 29 -
Figure 3-4 Parasitic capacitances at node, V . - 30 -
n

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List of figures

Figure 3-5 Mismatched current sources cell with a compensated non-
linear tranfer function (solid green line) by re-sequencing
the current source selections. - 34 -
Figure 3-6 Generalized DEM technique. - 34 -
Figure 3-7 Partial Random DEM (PRDEM) technique [16]. - 35 -
Figure 3-8 Random Multiple Data-Weighted-Averaging (RMDWA)
technique [17]. - 36 -
Figure 3-10 Randomized thermometer coding (RTC) technique [19]. - 38 -
Figure 3-11 Random swapping thermometer coding (RSTC) technique
[9]. - 39 -
Figure 3-12 Comparison of possible glitches occurring in each input
between Thermometer coding, DWA and OES [20]. - 40 -
Figure 3-13 Symmetrical switching schemes [21]. - 41 -
Figure 3-14 Hierarchical symmetrical switching schemes [22]. - 42 -
Figure 3-15 Q2 random walk switching schemes [23]. - 43 -
Figure 3-16 INL bounded switching scheme [6]. - 45 -
Figure 3-17 Self-calibrated DAC technique [24]. - 47 -
Figure 3-18 DAC with SSPA calibration technique [25]. - 49 -
Figure 3-19 DAC with complete-folding calibration technique [26]. - 50 -
Figure 3-20 DAC with DMM calibration technique [27]. - 52 -
Figure 3-21 DAC block diagram with 3D-SC calibration technique [28]. - 55 -
Figure 3-22 Comparison between Non-Return-to-Zero (NRZ) and
Return-to-Zero (RZ) [29]. - 56 -

Figure 4-1 Transfer function. (a) Ideal. (b) Mismatch. - 64 -
Figure 4-2 Output spectrum. (a) Ideal. (b) Mismatch. - 64 -
Figure 4-3 Current source cell selection with the conventional
thermometer- coded algorithm. - 65 -
Figure 4-4 Relation between glitch energy and number of switches. - 66 -
Figure 4-5 6 steps of SSPA calibration. - 68 -
Figure 4-6 Current source cell selection for OES. - 69 -
Figure 4-7 Graph of plotted data in Table 4-1. - 70 -
Figure 4-8 Investigated algorithm. - 71 -
Figure 4-9 Proposed calibration technique. - 72 -
Figure 4-10 Illustration of the process steps in the temporary memory,
LUT decoder and OES block. - 74 -
Figure 4-11 Error characteristics. - 76 -
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