Digit-Serial Computation

311 Pages·1995·9.089 MB·English

by  Richard Hartley, Keshab K. Parhi (auth.)

DIGIT-SERIAL COMPUTATION
TIlE KLUWER INTERNATIONAL SERIES
IN ENGINEERING AND COMPUTER SCIENCE
VLSI, COMPUTER ARCHITECTURE AND
DIGITAL SIGNAL PROCESSING
Consulting Editor
Jonathan Allen
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DIGIT-SERIAL COMPUTATION
by
Richard Hartley
eRD
General Electrical
Keshab K. Parhi
University 0/ Minnesota
~.
"
SPRINGER SCIENCE+BUSINESS MEDIA, LLC
ISBN 978-1-4613-5985-2 ISBN 978-1-4615-2327-7 (eBook)
DOI 10.1007/978-1-4615-2327-7
Library of Congress Cataloging-in-Publication Data
A C.I.P. Catalogue record for this book is available
from the Library of Congress.
Copyright © 1995 by Springer Science+Business Media New York
Originally published by Kluwer Academic Publishers, New York in 1995
Softcover reprint ofthe hardcover 1st edition 1995
All rights reserved. No part of this publication may be reproduced, stored in
a retrieval system or transmitted in any form or by any means, mechanical,
photo-copying, recording, or otherwise, without the prior written permission of
the publisher, Springer Science+Business Media, LLC
Printed on acid-free paper.
Contents
1 Digit-Serial Architecture 1
1.1 Data-Flow Architectures 1
1.2 Synchronous Circuits . . 2
1.3 Bit-Serial Architecture . 4
1.3.1 Comparison of Bit-Serial and Bit-Parallel Computation 7
1.3.2 Bit-Serial Circuit Architecture 8
1.3.3 Scheduling ... 9
1.3.4 Timing ..... 10
1.3.5 Previous Values. 11
1.4 Digit-Serial Architecture 14
1.4.1 Example Digit-Serial Circuit 16
1.5 Digit-Serial Operators . . . . . 18
1.5.1 Arithmetic Operators . 18
1.5.2 Comparison Operators. 19
1.5.3 Logic Operators 20
1.5.4 Constants.... 20
1.5.5 Delay Operators 21
1.5.6 Shift Operators . 22
1.5.7 Converters ... 22
1.5.8 Timing Signal Generation 22
1.5.9 Special Cells ....... 23
1.6 Layout Overview . . . . . . . . . 23
1.6.1 Bit-Slicing the Standard Cells. 24
1.6.2 Complete Chip Layout . 24
2 Digit-Serial Cell Design 27
2.1 Digit-Serial Layout . . . . . . . 27
2.1.1 The Standard Template 27
2.1.2 Delay Cells . . . . . . . 28
2.1.3 Deviation From The Standard Template. 30
2.2 The Add/Subtract/Compare Cell . 32
2.2.1 Division................... 34
VI CONTENTS
2.3 Digit-Serial Shifting 35
2.4 Cordie Operators 37
3 Multipliers 43
3.1 Multipliers ........ 43
3.2 Parallel Array Multiplier. 43
3.3 Bit-Serial multiplication . 44
3.3.1 Signed Multiplication 47
3.3.2 Serial Multiplication with Constant Word Length. 51
3.3.3 Size of the Multiplier. . . . 52
3.3.4 Constant Multiplication . . 53
3.3.5 Serial-Serial Multiplication 53
3.3.6 Software Support . . 54
3.4 Digit-Serial Multiplication . 54
3.5 Low Latency Multiplication 56
4 Digit-Serial Input Language 63
4.1 Cells........ 64
4.1.1 Leaf Cells . . . . 65
4.1.2 Stack Cells . . . 67
4.1.3 Composite Cells 68
4.1.4 Symbolic Cells . 68
4.2 Function Calls ..... 75
4.2.1 Adding New Functions. 78
4.3 Control Structures . . . 80
4.4 Standard Libraries . . . . . . . 82
4.4.1 Data Conversion . . . . 82
4.4.2 Parallel/Serial Conversion 83
4.4.3 Serial/Parallel Conversion 84
4.4.4 Latches . . . . . . . . . . 84
4.4.5 ROMs........... 85
4.4.6 Static and Periodic Signals 86
4.5 Examples . . . . . . . . . . 88
4.5.1 Square Root .... 88
4.5.2 Complex Arithmetic 90
5 Layout of Digit-Serial circuits 95
5.1 Digit-Serial Cell Layout Conventions 95
5.1.1 Layout of the Complete Chip 97
5.1.2 Linear Layout. . . . . . . . . 97
5.1.3 Two-Dimensional Placement . 100
5.2 Chip Examples . . . . . . . . . . . . . 102
CONTENTS vii
6 Scheduling 107
6.1 Scheduling................ . 107
6.2 Solving The Programming Problem. . . 113
6.3 Previous Values and Feedback Loops . . 117
6.3.1 Alternative Scheduling Method For z-l Operators . 118
6.4 Earliest-Possible Scheduling . . . . . . . . . . . . . 119
6.5 Swapping Multiplier Inputs . . . . . . . . . . . . . 123
6.6 Trees of Associative and Commutative Operators . 124
6.7 Algorithm for Optimizing Single Adder Trees . 126
6.8 Rearranging General Data-Flow Graphs . 129
6.9 Handling Subtractors . . . . . . . 131
6.10 Examples . . . . . . . . . . . . . 131
6.11 Why not other optimizations? . 134
7 Digit-Serial Performance 137
7.1 Ripple-Carry Operators . . . . . . . . . . . . 138
7.2 Look-Ahead Operators. . . . . . . . . . . . . 140
7.3 Improved Performance Through Unfolding. . 141
7.4 An Example. . . . . . . . . . . . . . . . . . . 144
8 Bit-Level Unfolding 147
8.1 Introduction............ . 147
8.2 Description of the Technique .. . 147
8.2.1 Operators With Latency. . 154
8.3 Collapsing Outputs. . . . . . . . . 157
8.4 Automatic Unfolding. . . . . . . . 158
8.5 Unfolding to Arbitrary Digit Sizes . 159
8.6 Parallel to Digit-Serial Converter . 160
9 The Folding Transformation 165
9.1 Introduction .................. . · 165
9.2 Digit-Serial Design Using Folding ...... . · 165
9.2.1 Pipelining and Retiming For Folding. · 167
9.2.2 Folding of Bit-Parallel to Bit-Serial and Digit-Serial Ar-
chitectures ............ . 169
9.3 Folding of Regular Data-Flow Graphs . . 171
9.4 Digit-Serial Architectures by Unfolding. . 175
10 Wavelet Transform Architectures 183
10.1 Introduction ........... . · 183
10.2 The Wavelet Computation ... . · 184
10.3 The Analysis Wavelet Architecture · 185
10.3.1 Life-Time Analysis. · 186
10.3.2 Register Allocation ..... · 191
Vlll CONTENTS
10.3.3 Digit-Serial Building Block . · 192
10.4 The Synthesis Wavelet Architecture · 193
11 Digit-Serial Systolic Arrays 195
11.1 Introduction. . . . . . . . · 195
11.2 Digit Serial Systolic Arrays · 197
11.3 Design Examples . . . . . . · 198
11.3.1 Convolution · 198
11.3.2 Band Matrix Multiplication · 201
11.4 The General Case - Theory . . . . · 203
11.4.1 Cell Specification . . . . . . · 203
11.4.2 Timing of the Whole Array .205
11.4.3 Generating Digit-Serial Arrays · 207
11.4.4 Expanding the Period . . · 208
11.5 Finding the Minimum Digit-Size · 211
12 Canonic Signed Digit Arithmetic 217
12.1 Canonic Signed Digit Format ......... . · 217
12.2 CSD Multiplication ............... . .220
12.2.1 Pushing Subtractions Towards the Root · 220
12.2.2 Size of Adders ... · 223
12.2.3 Error Computation. · 224
12.2.4 Bypassing Adders . .225
12.3 Sub-Expression Sharing . . .226
12.3.1 Finding Common Sub-expressions .227
12.3.2 Choice of Sub-expression · 230
12.3.3 An Example ........... . · 236
12.3.4 Routability ............ . .237
12.3.5 Using the Two Most Common Sub-expressions · 238
12.4 Carry-Save Arithmetic . . . . . . . . . . . . . . . .240
12.4.1 Carry-Save Subtraction ......... . · 242
12.4.2 Speed of a Carry-Save Multiplier Circuit. .243
12.4.3 Filters using Carry-Save Arithmetic .244
12.5 Asymptotic Occurrence of Pairs. ....... . . .246
12.5.1 Number of n-bit CSD integers. . .... . .246
12.5.2 Number of non-zero bits in CSD integers. .247
12.5.3 Restricting the range of CSD integers . .248
12.5.4 Asymptotic frequency of non-zero bits .. .249
12.5.5 Frequency of pairs. . . . . . .. .249
12.5.6 Asymptotic frequency of pairs. . . . . . · 251
CONTENTS
IX
13 Online Arithmetic 253
13.1 Redundant Data Formats . 253
13.2 Reduction of the Range of Digits . 255
13.3 Addition. . . . . . . . . . . . . . 261
13.4 An Alternative Implementation. . 262
13.5 Data Range and Overflow . . . . . 264
13.5.1 Reduction without Overflow Inhibition. . 266
13.5.2 Reduction with Overflow Inhibition .. . 267
13.5.3 Overflow with the Alternative Reduction Scheme . 267
13.6 Radix-2 Carry-Free Addition ... . 268
13.7 Data Format Conversion. . . . . . . . 271
13.7.1 Radix-2 Format Conversion . . 275
13.8 Radix-2 Multiplication Architectures . 275
13.8.1 Doubly-Redundant Multiplier Architectures . 276
13.8.2 Singly-Redundant Multiplier Architectures . 278
13.9 Radix-4 and Higher Radix Multiplication . 280
13.9.1 Constant Multiplication . . . . . . . . 280
13.9.2 Generalization to Higher Radices . . . 283
13.9.3 Variable-by-Variable Multiplication. . 288
Preface
Digital signal processing (DSP) is used in a wide range of applications such
as speech, telephone, mobile radio, video, radar and sonar. The sample rate
requirements of these applications range from 10 KHz to 100 MHz. Real time
implementation of these systems requires design of hardware which can process
signal samples as these are received from the source, as opposed to storing them
in buffers and processing them in batch mode. Efficient implementation of real
time hardware for DSP applications requires study of families of architectures
and implementation styles out of which an appropriate architecture can be
selected for a specified application. To this end, the digit-serial implementation
style is proposed as an appropriate design methodology for cases where bit-serial
systems cannot meet the sample rate requirements, and bit-parallel systems
require excessive hardware. The number of bits processed in a clock cycle
is referred to as the digit-size. The hardware complexity and the achievable
sample rate increase with increase in the digit-size. As special cases, a digit
serial system is reduced to bit-serial or bit-parallel when the digit-size is selected
to equal one or the word-length, respectively. A family of implementations can
be obtained by changing the digit-size parameter, thus permitting an optimal
trade-off between throughput and size.
Because of their structured architecture, digit-serial designs lend themselves
to automatic compilation from algorithmic descriptions. An implementation of
this design methodology, the Parsifal silicon compiler was developed at the
General Electric Corporate Research and Development laboratory. Parsifal
constitutes a complete design environment, including capabilities for simula
tion, fault-simulation, chip layout, layout verification and timing verification.
However, this book limits itself to a description of the digit-serial architecture
and design and layout synthesis methods used in Parsifal.
The book goes beyond a description general digit-serial architectures (as
embodied for instance in Parsifal) to discuss some wider-ranging issues in digit
serial design. We discuss systematic methods for the design of digit-serial
architectures and design elements in chapters on "folding" and "unfolding".
In addition we include chapters on systolic arrays, canonic-signed-digit num
ber representation and carry-save arithmetic from the viewpoint of digit-serial
arithmetic.
The emphasis of the book is on least-significant-digit (LSD) first digit-serial
computation. However, much of the material applies as well to most-significant
digit (MSD) first arithmetic. MSD-first digit-serial arithmetic is often called on
line arithmetic, and has been a popular area of research. In on-line arithmetic, a
redundant number representation is necessary to allow computation to proceed
in a most-significant-bit first manner. The carry-free property of redundant
number based architectures makes them ideal for high-speed implementation of
DSP algorithms involving feedback loops, where minimization of loop latency is