Design Techniques For Delta Sigma Modulators Using VCO Based ADCs

96 Pages·2014·2.59 MB·English

AN ABSTRACT OF THE DISSERTATION OF
Karthikeyan Reddy for the degree of Doctor of Philosophy in Electrical and
Computer Engineering presented on March 10, 2014.
Title: Design Techniques For Delta Sigma Modulators Using VCO Based ADCs
Abstract approved:
Pavan Kumar Hanumolu
VCO-based ADCs have recently emerged as attractive alternative to conven­
tional Delta Sigma (ΔΣ) modulator architectures. Few salient features of a VCO­
based ADC are: 1) the quantization noise is 1st order noise shaped, 2) it is an open
loop architecture, and, 3) its implementation is mostly digital in nature. Hence,
they are ideally suited for oversampled data converter techniques with the capa­
bility to operate at near GHz frequencies. However, their performance is severely
limited by the non-linearity of the voltage to frequency transfer curve. Also, when
operating at GHz frequencies, the excess loop delay (ELD) of a continuous-time
ΔΣ modulator can be a large fraction of the sampling period, thereby affecting the
of stability of the modulator. In this work, two new architectures are proposed to
overcome the above mentioned drawbacks.
In the first approach, a continuous-time Delta Sigma modulator incorporates a
non-linear VCO as the second stage in a 2-stage residue canceling quantizer (RCQ)
and mitigates the impact of its non-linearity by spanning only a small region of
the VCOs tuning curve.
In the second approach, both phase and frequency domain information are
extracted from the VCO and fedback, which provides an extra clock cycle delay in
the feeback path. This relaxes the timing constraints for the modulator, allowing
it to be clocked at GHz frequencies.
©cCopyright by Karthikeyan Reddy

March 10, 2014

All Rights Reserved
Design Techniques For Delta Sigma Modulators Using

VCO Based ADCs

by

Karthikeyan Reddy

A DISSERTATION

submitted to

Oregon State University

in partial fulfillment of

the requirements for the

degree of

Doctor of Philosophy

Presented March 10, 2014

Commencement June 2014
Doctor of Philosophy dissertation of Karthikeyan Reddy presented on
March 10, 2014.
APPROVED:
Major Professor, representing Electrical and Computer Engineering

Director of the School of Electrical Engineering and Computer Science

Dean of the Graduate School
I understand that my dissertation will become part of the permanent collection
of Oregon State University libraries. My signature below authorizes release of my
dissertation to any reader upon request.
Karthikeyan Reddy, Author
ACKNOWLEDGEMENTS
My student life at Corvallis has been very enriching and eventful. I have had the
opportunity to not only enhance my research knowledge, but I have also gained
insight into the culture of a new place. I have had the opportunity to interact with
some of the nicest and brighest people. I would always cherish those moments.
This work would not have been possible without the unwavering support of my
advisor, Dr. Pavan Kumar Hanumolu. He has stood by me during my lean times
and I am very much indedbted to him for the faith he has reposed in me. He has
been indefatigable in his pursuit of excellence, eliciting the same qualities from his
students. Inspite of his busy schedule, he has always found time to interact and
engage in long discussions with his students. I would like to thank him for all the
guidance he has provided during my stay at Oregon State University.
I would like to thank Prof. Un Ku Moon, Prof. Gabor Temes and Prof. Kar­
tikeya Mayaram for being my committee members. I would also like to thank Prof.
Merrick Haller for being my Graduate Committee Representative. I would like to
thank Prof. Bella Bose for the help extended in the absence of Prof. Hanumolu in
the final year of studies. As the graduate program coordinator, Ferne Simendinger
and later Nicole Thompson were very helpful with all the paper work needed for the
program. Thanks Todd Shechter for providing all the services related to computer
and softwares.
My life on campus would not be complete without the wonderful friends I made
here. Rajesh Inti (IR) has been instrumental in bringing me to OSU. Thanks to
Sachin and Brian Young for all the technical discussions that we have had. I
am fortunate to have Mrunmay, Amr, Praveen, Saurabh, Romesh, Brian Drost,
Guanghua and Tejasvi as my friends and colleagues. Thank you all for helping
me during design, tapeout, testing and documentation. I would also like to thank
my friends Manideep, Hariprasath, Ankur, Siladitya, Jason, Farshad, Jerry and
Spencer with whom I spent some wonderful moments. Thanks Ankur for proof­
reading my thesis. Thanks to my undergrad friends, Arun and KG, whose support
I have always had. Thanks to Vikas and family, Ravindranath and family for
being good friends and wonderful neighbours. Thanks to all whom I would have
unintentionally missed in this list.
I would like to thank Cesign for supporting my research work. I would like to
thank Alessandro Piovocarri, Ramin Poorfard and Abdulkerim Coban who pro­
vided the opportunity to work as an intern at Silicon Labs. I would like to thank
Prof. ShanthiPavanwhohadintroducedmetotheworldofanalog design. I would
like to thank Prof. P.V. Ramakrishna who was my mentor at Anna Unviersity.
My journey has not been without any hurdles. Several people have been in­
strumental in helping me during the phase when I was not well. I would like to
thank Namita Mayaram for the encouraging words and the advice and tips for a
healthy lifestyle. I would like to thank Kottakal Arya Vaidya Sala and Prithviraj
for the therapies which rejevenated my health.
This work would not have been possible without the unconditional love and
support of my parents, wife and extended family. My parents Krishna Mohan and
Meenakshi have always been encouraging and supportive of me. I owe a lot to
them for their sacrifices in bringing up my sister and me. My wife Jayashree has
been a pillar of support and I cannot possibly imagine doing any of this without
her. She has been my best friend, companion and caretaker. For the past year,
she has been taking care of our baby, Abhinaya, in my absense and she has been
wonderful at it. I would like to thank my sister Jayalakshmi, grandparents, uncles
Krishna Kumar, Sathya Narayanan and Kumar Prasad and aunts Vasuki Prasad
and Latha for their love and support.
TABLE OF CONTENTS

Page

1 INTRODUCTION 1

1.1 Scope of this work . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

1.2 Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2 VOLTAGE CONTROLLED OSCILLATOR BASED ADCs 5

2.1 Prior Solutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.1.1 Digital Background Calibration . . . . . . . . . . . . . . . . 11

2.1.2 Two level Modulation of VCO input . . . . . . . . . . . . . . 12

2.1.3 ΔΣ Modulator utilizing a VCO based ADC . . . . . . . . . . 13

3 CONTINUOUS TIME ΔΣ MODULATOR USING A RESIDUE CAN­
CELLING QUANTIZER 16

3.1 Proposed Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.1.1 Limitations of Residue Canceling Quantizer . . . . . . . . . 18

3.1.2 Mitigation of RCQ Errors Using ΔΣ Feedback . . . . . . . . 21

3.2 Prototype Continuous-time ΔΣ Modulator . . . . . . . . . . . . . . . 25

3.3 NTF of the modulator . . . . . . . . . . . . . . . . . . . . . . . . . . 27

3.4 Schematic Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.4.1 VCO Quantizer . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.4.2 Loop filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

3.4.3 Four-bit Flash Quantizer (ADC ) . . . . . . . . . . . . . . . 34

F
3.4.4 Digital to Analog Converters (DAC and DAC ) . . . . . . 35

M F
3.5 Measurement results . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

4 CONTINUOUS-TIME ΔΣ MODULATOR USING PHASE-FREQUENCY
FEEDBACK TECHNIQUE 45

4.1 VCO as a Phase quantizer . . . . . . . . . . . . . . . . . . . . . . . . 46

4.2 Impact of Excess Loop Delay on the stability of the Modulator . . . . 49

4.2.1 Upper limit on the sampling frequency . . . . . . . . . . . . 52

4.3 Proposed Phase-Frequency architecture . . . . . . . . . . . . . . . . . 54

4.4 Prototype ΔΣ Modulator . . . . . . . . . . . . . . . . . . . . . . . . 56