Design of High-Performance CMOS Voltage-Controlled Oscillators

169 Pages·2003·9.05 MB·English

by  Liang Dai, Ramesh Harjani (auth.)

Design of High-Performance CMOS
Voltage-Controlled Oscillators
THEKLUWER INTERNATIONAL SERIES IN ENGINEERING
AND COMPUTERSCIENCE
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ConsultingEllitor: Mohammed Ismail. O"ioState University
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DESIGN OF HIGH-PERFORMANCE CMOS
VOLTAGE-CONTROLLED OSCILLATORS
LIANGDAI
Prominent Communications, Inc.
San Diego, California, USA
RAMESH HARJANI
Department of Electrical and Computer Engineering
University of Minnesota
Minneapolis, Minnesota, USA
Springer Science+Business Media, LLC
Library of Congress Cataloging-in-Publication Data
Liang Dai & Ramesh Harjani
Design of High-Performance CMOS Voltage-Controlled Oscillators
ISBN 978-1-4613-5414-7 ISBN 978-1-4615-1145-8 (eBook)
DOI 10.1007/978-1-4615-1145-8
Copyright © 2003 by Springer Science+Business Media New York
Originally published by Kluwer Academic Publishers in 2003
Softcover reprint ofthe hardcover Ist edition 2003
AII rights reserved. No part ofthis work may be reproduced, stored in a retrieval
system, or transmitted in any form or by any means, electronic, mechanical,
photocopying, microfilm ing, record ing, or otherwise, without the written permission
from the Publisher, with the exception of any material supplied specifically for the
purpose of being entered and executed on a computer system, for exclusive use by
the purchaser of the work.
Printed an acid-free paper.
Contents
ListofFigures IX
ListofTables xv
Preface xvii
Acknowledgments xix
1. INTRODUCTION 1
2. INTRODUCTIONTOPLLS 9
1 Introduction 9
2 PLLBasics 10
3 ALinear~odelforPLLs 18
4 Conclusions 26
3. PHASENOISE ANDTIMINGJITTER 27
1 Phase Noise 27
2 TimingJitter 30
3 Phase Noise vs. Timing Jitter 33
4 Conclusions 37
4. REVIEW OFEXISTING VCO PHASENOISE~ODELS 39
1 Challenges in OscillatorPhase Noise Analysis 39
2 Leeson's~odel 40
3 Razavi's ~odel 46
4 Hajimiri's ~odel 49
5. UNIVERSALMODELFORRINGOSCILLATOR
PHASE NOISE 55
1 Comparison and AnalysisofRing OscillatorPhaseNoise 55
DESIGNOFHIGH-PERFORMANCECMOS VCOS
1.1 VCOCircuitDiagrams 56
1.2 PhaseNoise Analysis 56
1.3 MeasurementResults 61
2 ModifiedLinearModel 63
2.1 TheoreticalAnalysis 64
2.2 SimulationResults 68
2.3 MeasurementResults 69
3 Q-factorforRing Oscillators 71
4 Noise Up-Conversion 74
4.1 TheoreticalAnalysis 75
4.2 Simulation Results 78
4.3 MeasurementResults 80
5 PowerSupply/ SubstrateNoise 81
5.1 TheoreticalAnalysis 81
5.2 SimulationResults 83
6 Conclusions 85
6. NEW RINGVCODESIGN 87
1 Introduction 87
2 PhaseNoiseOverview 87
3 CircuitDesign 89
4 AnalysisofCircuits with Hysteresis 92
5 Simulation and Measurement 100
6 Conclusions 106
7. PLLDESIGNEXAMPLES 107
1 PLLwith Ring VCO 108
1.1 Ring VCO 108
1.2 ChargePumpandLoopFilter 109
1.3 PhaselFrequencyDetector 119
1.4 PrescalerandFrequencyDivider 120
2 LCVCO 126
3 Simulation Results 136
4 MeasurementResults 142
5 Conclusions 145
8. CONCLUSIONS 149
1 ResearchContributions 149
Contents
2 Summary 150
List ofFigures
1.1 Weaverimagereject receiver 2
1.2 A simplified block diagram for clock/data recovery circuits 4
1.3 Cross talkdue to phase noisefor wireless receivers 5
1.4 Aparallel resonator 6
1.5 Aring oscillator 6
2.1 Illustration ofaPLLwith N = 3 9
2.2 A simplified blockdiagram for atypical PLL 10
2.3 Characteristics ofa multiplierasa PD 11
2.4 Characteristics ofan XORgateas aPD 12
2.5 Aphase/frequency detector (PFD) 13
2.6 AchargepumpPLL 14
2.7 Example inputs and outputs for PPD (a) IR < Iv (b)
V is lagging R 14
2.8 Illustration ofdead zone 15
2.9 PD characteristics with dead zone 16
2.10 Elimination ofdead zone (a) with zero phase error (b)
with finite phase error 17
2.11 Periodic output current from the charge pump due to
current mismatch 17
2.12 A linearmodel for aPLLin locked state 18
2.13 A linearmodelfor achargepumpPLLwith noise sources 20
2.14 APLLopen-loop transfercharacteristic withand with-
out lead-lag compensation 21
2.15 Comparison ofclosed-loop andopen-loop responsefor
acharge pumpPLL 22
DESIGNOFHIGH-PERFORMANCECMOS VCOS
2.16 Derivation ofnoise transfercharacteristic for VCO 23
3.1 Illustration ofphase noise and timingjitter 28
3.2 Definition ofSSB phasenoise 29
3.3 A typical spectrum for SSB phasenoise 29
3.4 Jitter measurement (a) self-referred (b) input-referred 31
3.5 Self-referredjitterofastand-alone VCO 32
3.6 Self-referredjittervs. time interval for a VCO 32
3.7 Self-referredjittervs. time interval for aPLL 33
4.1 A linearfeedback system 39
4.2 RLC parallel network 41
4.3 Magnitude ofthe impedance across the RLC tank 42
4.4 Modelfor an LC tank with an activedevice - R 43
4.5 Additive noise to phasenoise conversion 45
4.6 PSD plots for inputdevice noiseand phase noise 46
4.7 Barkhausen criteria 47
4.8 Waveforms in a 3-stagering oscillator 49
4.9 Perturbation ofvoltage waveform due to a current im-
pulse at(a) the zerocrossing (b) peak 50
5.1 Differential inverterwith Maneatis loads 57
5.2 Differential inverter with single PMOS loads 57
5.3 Coupled ring oscillator(a) inverter stage (b) strongand
weak inverters (c) weighted current adder(d) Vcntrl generator 58
5.4 Current-starved inverteroscillator 58
5.5 Internaldifferential voltage waveformsforringoscilla-
tors with Maneatis load, saturation loadand triode load 60
5.6 Diephotograph ofthe testchip 62
5.7 SSB phasenoise ofthe ring oscillators 63
5.8 Modified linearmodelfor a 3-stage ring VCO 64
5.9 Sinusoidal waveform clipped by powersupplies 65
5.10 Waveform with softslipping 66
5.11 SSB phase noise vs. VPP 68
5.12 The bias and a delay cell for a ring oscillator with a
source coupled pairand symmetric loads 70
5.13 A three-stagecoupled ring oscillator 70
5.14 Chip microphotographs for (a)Maneatis ring oscillator
(b)coupled ring oscillator 71
ListofFigures
5.15 SSBphasenoisecomparisonbetweentheManeatisos-
cillator andthecoupled ring oscillator 72
5.16 Effective Qfactor asafunction ofthe IT ofthe process 74
5.17 Bias structure for an N-stagering oscillator 75
5.18 Up-conversion mechanism for low frequency noise in
the tail and bias 76
5.19 Thebias and adelay cell for a three-stage ring oscillator 79
5.20 Simulation offrequency variation vs. bias current variation 79
5.21 Phasenoise withdifferent by-pass capacitors 80
5.22 AVCOblockdiagram (a) traditional view (b) arigorous view 81
5.23 Athree-stage differential ring oscillator 82
5.24 Waveformsshowingthesixequivalentstatesforathree
stage oscillator 82
5.25 Sideband PSD when sinusoidal ripple is added to the
power supply 84
6.1 Illustration ofmajornoise sources in a traditional fully
differential ring oscillator 88
6.2 VCO schematic (a) top-level (b) logic-level for delay
cells (c) transistor-level fordelay cells 90
6.3 ChannelresistanceofanNMOStransistorwithVds = 0
vs. gate voltage. 91
6.4 A simplified delay cell withoutdelay control 92
6.5 Anexample casefor astepresponse 93
6.6 Thethreshold ofthedelay cell as afunction of(32/(31 94
6.7 Simulated hysteresis curve for the delay cell 94
6.8 An N-stage ring oscillator with hysteresis delay cells 95
6.9 Waveforms atnodes aand binFigure6.8 95
6.10 T/(RC) as afunction oflith/V for a2-stage ring oscillator 97
dd
6.11 Sensitivity ofperiod with respect to threshold voltage
for a 2-stagering oscillator 98
6.12 T/(RC) as afunction oflIth/Vdd for a3-stage ring oscillator 99
6.13 Sensitivity ofperiod with respect to threshold voltage
for a3-stage ring oscillator 99
6.14 Waveforms forring oscillators withdifferent numberofstages100
6.15 Quadrature output waveforms 100
6.16 Diephoto 101
6.17 Circuitboardfor VCO testing 101
6.18 Measured control characteristic for thering VCO 102