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Reference Matlab code is available at sites.google.com/site/shahriarshahabuddin/matlab simulator Design of a Transport Triggered Architecture Processor for Flexible Iterative Turbo Decoder Shahriar Shahabuddin, Janne Janhunen, and Markku Juntti Department of Communications Engineering and Centre for Wireless Communications, University of Oulu, Finland. {sshahabu, janne.janhunen, markku.juntti}@ee.oulu.fi 5 1 0 Abstract—Inordertomeettherequirementofhighdatarates hardwaretogethertogrindoutthebestperformanceandensure 2 for the next generation wireless systems, the efficient implemen- programmability is not a straightforward task. The designer tation of receiver algorithms is essential. On the other hand, needs a very efficient tool, which can be used to design the n the rapid development of technology motivates the investigation a processor easily for a particular application. of programmable implementations. This paper summarizes the J design of a programmable turbo decoder as an application- In this paper, we propose a design of a processor based 7 specific instruction-set processor (ASIP) using Transport Trig- on the Transport Trigger Architecture (TTA) for a flexible 1 geredArchitecture(TTA).Theprocessorarchitectureisdesigned turbo decoder. TTA is a very good processor template for in such manner that it can be programmed to support other a programmable application-specific instruction-set processor ] receiver algorithms, for example, decoding based on the Viterbi R (ASIP). The TTA based codesign environment (TCE) tool algorithm. Differentsuboptimalmaximuma posteriori (MAP) A algorithms are used and compared to one another for the soft- enables the designer to write the application with high level . input soft-output (SISO) component decoders in a single TTA language and design the target processor in a graphical user s processor. The max-log-MAP algorithm outperforms the other interface at the same time [3]. c suboptimal algorithms in terms of latency. The design enables [ The turbo decoder based on the transporttriggred architec- the designer to change the suboptimal algorithms according to ture was implemented by Salmela et al. [4]. The throughput 1 thebiterrorrate(BER)performancerequirement.Unlikemany v other programmable turbo decoder implementations, quadratic oftheprocessorwascomparabletothoseoftheturbodecoders 2 polynomial permutation (QPP) interleaver is used in this work based on a pure hardware design, but was less flexible in 9 for contention-free memory access and to make the processor comparison with the design presented in this paper. The 1 3GPP LTE compliant. Several optimization techniquesto enable interleaver of the processor was not presented according to 4 realtimeprocessingonprogrammableplatformsareintroduced. the 3GPP LTE standard. 0 Usingourmethod,withasingleiteration31.32Mbpsthroughput . isachievedforthemax-log-MAPalgorithmforaclockfrequency The focus of the turbo decoder processor design in this 1 of 200 MHz. paper is flexibility. The quadratic permutation polynomial 0 (QPP) interleaving pattern have been used for the interleaver 5 I. INTRODUCTION block. The comparison with the other suboptimal algorithms 1 : The turbo coding scheme [1] has been adopted for the air likelog-MAP,constant-log-MAPandlinear-log-MAPhasalso v interfacestandardcalledLongTermEvolution(LTE),thathas been presented. i X beendefinedbythe3rdGenerationPartnershipProject(3GPP) The rest of the paper is organized in the following way: r [2]. The decoding algorithm for the component decoder is In Section II, an overview of the turbo decoder has been a not specified by 3GPP. Different suboptimal algorithms have presented. In Section III, the simplification techniques of been used for the turbo decoding and new solutions with less the turbo decoding algorithm and its implementation in high complexity are still being invented quite frequently. A pro- level language is presented. The processor design has been grammable implementation simplifies the necessary support presented in Section IV. In Section V, we will present the fordifferentsuboptimalalgorithmsofcomponentdecodersand throughput results of the design. The conclusion is given in different interleaving methods. Section VI. The turbo decoding algorithm is still one of the most II. TURBO DECODER computationally intensive parts of the wireless receiver. The A. Turbo Decoder Structure software implementations provide the required flexibility to support multistandard solutions, but requires a careful design The turbo decoder consists of two soft-input soft-output to achieve the target throughput. On the other hand, the (SISO)decoders,withinterleaversandde-interleaversbetween hardware implementations provide high throughput, but the themasshowninFig.1.Theinputsoftheturbodecodercome developmenttimeisnotasrapidasprocessorbasedimplemen- from the soft demodulator,which producesthe log-likelihood tations. Programmable accelerators, which enable software- ratios(LLR)forthe systematic bits andparitybits. The LLRs hardware co-design method might be an attractive solution ofthesystematicbit,LuIandfirstparitybits,LcI1goestothe to overcome these bottlenecks. The design of software and first SISO decoder. The SISO decoder produces soft outputs Reference Matlab code is available at sites.google.com/site/shahriarshahabuddin/matlab simulator based on these LLRs. These soft outputs are used in the 4. Calculate all the backward state metric of the same secondSISOdecoderastheadditionalinformation.Theinputs window through the backward recursion as osyfsttheme asteiccobnidts,SsIeScOonddepcoardietyr baritestdheenoLtLedRsbycoLmcIi2nganfdroomutpthuet βk(s)=max∗(βk+1[sE(e)]+u(e)LuI[k+1] (2) ofthefirstSISO decoder.TheLLRsofthe systematicbitsare +c1(e)LcI1[k+1]+c2(e)LcI2[k+1]). scrambledthistime with thesame interleavingpatternusedat 5. The LLR values for the information and both parity bits the encoder. Similarly, the soft outputs coming from the first can be calculated as following: SISO decoder are scrambled also with the same interleaving pattern,whichareusedasapriorivaluesforthesecondSISO LLR(.;O)=max∗(αk−1[sS(e)]+c1(e)LcI1[k−1] (3) decoder. +c2(e)LcI2[k+1]+βk+1[sE(e)]). The forward metric and backward metrics increase in each step and that is why the forward and backward metrics need to be normalized to avoid memory overflow. The decoding is done in smaller windows so that the decodingprocesscanbedoneinparallelandthedecoderdoes not have to wait for the whole block to arrive before starting the decoding process. This windowing is sometimes referred to as a sliding window method. Basedonthedefinitionofthemax∗function,thesuboptimal algorithms can be changed for the MAP algorithm. As for an example,for constant-log-MAPalgorithm it can be expressed as 0 if|y−x|>T ∗ max (x,y)=max(x,y)+ (4) (C if|y−x|≤T. We considered four suboptimal MAP algorithms, which are Max-log-MAP,constantlog MAP, linear-log-MAPand an ap- Fig.1. Blockdiagram oftheturbodecoder. proximationoflog-MAPalgorithm.Amoredetailedoverview The heart of the turbo coding is the iterative decoding of these algorithms can be found in [6], [7] and [8]. procedure. The output of the second SISO decoder does not C. QPP Interleaver produce the hard outputs immediately, but the soft output is used again in the first SISO decoder for more accurate The QPP interleaver has been adopted for the 3GPP LTE approximation. The process continues in a similar fashion in standard[3].Unliketheearlier3Ginterleavers,theQPPinter- aniterativemanner.Asingleiterationbyboththefirstandthe leaverisbasedonalgebricconstructions.The QPPinterleaver second SISO decoder is referred to as a full iteration. On the can be expressed by a simple mathematical formula. The otherhand,theoperationperformedbyasingleSISOdecoder relationship between the output index x and the input index can be referred to as a half iteration. At the beginning of the f(x) can be derived from this formula given below first iteration, the a priori values are set at zero. Six to eight full iterations are used to achieve sufficient performance [1]. f(x)=(f2x2+f1x)mod(N). (5) Thevaluesoftheparametersf1 andf2 of(5)areintegersand B. MAP algorithm for Component Decoder dependon the blocksize N. For a differentN, a differentset of parameters have been defined in [9]. The block sizes are TheMAPalgorithmforthecomponentdecoderappliedhere divisible by 4 and 8. The value of f1 is an odd numberwhile hasbeenproposedbyBenedettoet al. [5].Thealgorithmcan the value of f2 is an even number.Severalalgebric properties be stated like: of QPP interleaver have been listed in [10]. 1.Initializethevaluesoftheforwardstatemetricasα0(s)= 0 if s=S0 and α0(s)=−∞ otherwise. III. DESIGN IN HIGH LEVELLANGUAGE 2.Calculatealltheforwardstatemetricofthesamewindow The MAP algorithm described above is complexand needs through the forward recursion according to to be simplified. The repeated calculationsshouldbe avoided, which in turn reduces the latency of the processor. The αk(s)=max∗(αk−1[sS(e)]+u(e)LuI[k−1] reduced calculations used in this work will be described in (1) +c1(e)LcI1[k−1]+c2(e)LcI2[k−1]). the following section. The reduced design has been tested in a link level simulator using Matlab. The Matlab design 3. Initialize the values of the backward state metric as is converted to C language in such a way so that it can be β (s)=0 if s=S and β (s)=−∞ otherwise. efficiently implemented in the TCE tool. n n n Reference Matlab code is available at sites.google.com/site/shahriarshahabuddin/matlab simulator metrics have been calculated first in this design by following the simplified equation. The normalization technique is done followingthetechniquesuggestedbyValentiet al. [12].Typ- ically, the normalization is done in every step by subtracting the minimum values of forward or backward metrics of the same column from every forward or backward metric values. Theysuggestedsubtractingall the valuesfromthe first values of the columns. Thus, there is no need to store the first row andthisconstitutes12.5percentsavingsinmemorycompared with the other normalization methods. Only the forward metrics are saved for the calculation of the LLRs. The backward metrics and LLR calculations are done together. As soon as the backward metric calculations of a single column are finished, the LLRs are calculated in parallelwith thehelpofthe storedforwardmetricatthesame time. So there is no need to save the backward matrics [12]. Originally, α and β are two-dimensional matrices of size 6144× 8 as the input block of 6144 information bits have been taken into consideration. The processor needs to do morecalculationforaccessingthesetwodimensionalmatrices. Instead of using a single 6144×8 matrix, seven vectors of 6144elementshavebeenused.Asmentionedabove,theeighth vectorisnotneededduetothenormalizationstrategyadopted in the used method. Fig.2. Trellisof3GPPturbocode. The turbo decoder description in C needs to be efficient to fulfillthelatencyrequirement.A lotofdata dependenciescan beseenfromtheturbodecoderalgorithm.So,writingefficient Thereare16branchmetriccomputationsbetweentwostates code is needed for the utilization of computing resources for forward metric, backward metric and LLR calculations. available. From the trellis structure of the 3GPP turbo code it can be Assuming thatenough register files are available, efficient seenthatfourcalculationsofbranchmetricarebeingrepeated code is written to reduce memory accesses by holding the to result in total sixteen calculations. Instead of multiplying values inside the register files. It is also possible to eliminate with 1 and −1, the branch metrics can be calculated directly the need for accessing the forward metric vectors constantly. based on these four calculations, Instead, the temporary variables are used to hold the values γ1 =LuI+LcI1+LcI2 insidethe registers.Thecodeforthe backwardmetricandthe LLR calculations have been written in the same manner. The γ2 =−LuI−LcI1+LcI2 (6) calculations are done is several smaller loops to follow the γ3 =LuI+LcI1−LcI2 sliding window technique and to enable parallel calculations. γ4 =−LuI−LcI1−LcI2, A look-up table, holding the values of the f1 and f2 whereγ4 canberepresentedas−γ1 andγ3 canberepresented parameters, is used to implement the QPP interleaver. The as−γ2.Foreveryforwardmetric,thebackwardmetricandthe rest of the calculations are quite straightforward. LLR, calculations of two branch is sufficient. As an example, the backward metric calculations are shown as, IV. TRANSPORT TRIGGERED ARCHITECTURE PROCESSOR ∗ A. General Functional Units β1(k)=max (β1(k+1)−γ1,β5(k+1)+γ1) β2(k)=max∗(β1(k+1)+γ1,β5(k+1)−γ1) A part of the processor designed for the turbo decoder ∗ is illustrated in Fig. 3. For readability, the whole processor β3(k)=max (β6(k+1)+γ2,β2(k+1)−γ2) figure is not given.The blocks on the upper part of the figure ∗ β4(k)=max (β6(k+1)−γ1,β2(k+1)+γ1) representthefunctionalunitsandregisterfilesoftheprocessor. (7) ∗ β5(k)=max (β1(k+1)−γ1,β5(k+1)+γ1) The black horizontal straight lines represent the buses of β1(k)=max∗(β1(k+1)−γ1,β5(k+1)+γ1) the processor. The vertical rectangular blocks represent the ∗ sockets.The connectionbetweenfunctionalunitsand busesis β1(k)=max (β1(k+1)−γ1,β5(k+1)+γ1) illustrated by black spots in the sockets. ∗ β1(k)=max (β1(k+1)−γ1,β5(k+1)+γ1). The fixed point processor includes load/store unit (LSU), Asimilarideahasbeenpresentedin[11]whereasimplified arithmetic logic unit (ALU), global control unit (GCU) and version of max-log-MAP has been proposed. The forward registerfiles.Basedontheresourcerequirementsinhighlevel Reference Matlab code is available at sites.google.com/site/shahriarshahabuddin/matlab simulator Fig.3. Implemented processorwithreduced numberoffunctional units. language, more functional units and register files have been The forward and backward metrics calculations are not the added. same. The inputs and outputs of the unit need to be selected The LLR inputs have been read from a first-in-first-out carefullybecausethesameunithasbeenusedforbothforward (FIFO) memory buffer by using the functional unit called and backward metric computations. Using the same unit for STREAM. The STREAM units can read every input sample forwardandbackwardmetriccomputationsispossiblebecause in one clock cycle. Eight STREAM units have been used to of the trellis structure of a 3GPP turbo code. get the input LLRs simultaneously. The STREAM units are The design of the Metric unit for one butterfly pair in used to implement the sliding window technique that helps the trellis is shown in Fig. 4. The values of branch metrics to decode the input block in smaller parts parallely. One to calculate α2(k) and β3(k) are the same. Likewise, the STREAM unit has been used to write the output LLRs in values of branch metrics to calculate α6(k) and β4(k) are the memory buffer. also the same. It is possible to calculate these forward and Three LSU units have been used to support the memory backward metrics by changing the input values of the earlier accesses. The LSU units are used to read and write memory. state metrics. This is true for all the rest of the butterfly The memory can be read in three clock cycles and can be pairs in the trellis. The METRIC unit uses this technique of written in a single cycle. changing the orders of the input metrics for the backward The ALU unit has been used to perform the basic arith- metrics calculation, but using the same function unit. meticoperationslikeaddition,subtractionetc.Operationslike The METRIC unit supports four operations. These four shifting right or left are also included in ALU. operations are branch metric calculations for max-log-MAP, linear-log-MAP,constant-log-MAPandlog-MAPrespectively. B. METRIC Special Function Unit The latency of these operations are different because these operations use different codes for different algorithms. LiketheViterbidecoder,theturbodecoderneedsnumerous add-compare-selectoperations.Onewaytodesigntheproces- C. MAX7 Special Function Unit sor for these algorithms is to use the appropriate number of adderandmaximumselectionunits. Anotherway is todesign Another special function unit named MAX7 has been a specialfunctionunitto calculate all the necessarynextstate designed, which is used to calculate the output LLRs after metrics based on the earlier state metrics and branch metrics. the forward and backward metrics computation. This unit The latter way is followed in our design and a special also has four options for four suboptimal algorithms. For the function unit named METRIC has been designed with twelve max-log-MAP mode, the MAX7 unit takes seven inputs and inputs and eight outputs. Eight of these inputs correspond to findsthe maximumof these inputs. The LLR calculation uses the forward metrics in case of forward metric calculations the maximum value of seven computations in this case. The andbackwardmetricsincaseofbackwardmetriccalculations. addition of the forward metric, branch metric and next state ThreeoftheseinputscorrespondtotheaprioriLLR,theLLR backwardmetricrepresentthesecomputations.Itispossibleto ofsystematicbitsandtheLLRofparitybits,respectively.One reduce one computationbecause of the normalization method inputisusedtoselectdifferentsuboptimalalgorithmsandthis choseninthisdesign.Wehavegiventheaddedvaluesofthese input is named mode in this paper. sevencomputationsasinputstothisunitandusedtheoutputas Reference Matlab code is available at sites.google.com/site/shahriarshahabuddin/matlab simulator reason lies in the fact that the constant-log-MAP, linear-log- MAP and log-MAP algorithms need to invoke some condi- tionalstatements resultingin branchesin execution.Thus,the latency increases compared to the max-log-MAP algorithm. A less complicated approximationof log-MAP has been used in this design. However, the correction term of the log-MAP increasesthe latency significantlycomparedto the other three suboptimal algorithms even after the simplification. Linear- log-MAP is slower than the constant-log-MAP because of some multiplication operations are needed. The log-MAP algorithmprovidesbetter BER performancethan the other al- gorithms.Thislog-MAPcanbeusedincaseswhenthelatency requirements are not strict and a high BER performance is needed. Fig.4. METRICunitforasinglebutterflypair. The buses of the processor are perfectly utilized to achieve thebestpossibleresultduetotheperfectscheduling.Thenum- ber of some of the operations during the algorithm execution theLLR.Thelatencyofthisunitisdifferentforfourdifferent has been summarized in Table II. algorithms. D. Registers TABLEII NUMBEROFOPERATIONS Severalregisterfileshavebeenusedtosavetheintermediate results. In terms of the power consumption, registers can Operation #ofOPS be more expensive than memory, but to meet the latency ADD 339,009 SUB 98,304 requirementregisterfilesareneeded.AsingleBooleanregister MUL 45,234 file has been included in the processor design. MAX7 24,567 BRANCH 24,576 V. RESULTS ANDDISCUSSION STREAM 24,556 Thedesignedprocessortakes39,226clockcyclestoprocess three blocks of 6,144 samples for a full iteration for the max- The number of addition operations does not only represent log-MAP mode. According to the 3GPP interleaver specifica- the addition for the algorithm, but for several other purposes tions, the size of the block could be up to of 6,144 samples like loop indexing for the code. The subtraction operations and that is the reason the size of the input block is chosen as aredueto the normalizationandthe multiplicationis usedfor 6,144. the correction term calculation of linear-log-MAPand for the When we assume a clock of 200MHz, thenthe throughput QPP interleaving sequence generation. of one iteration for the max-log-MAP could be calculated as, The throughput can be increased using dedicated special 6,144bits×200MHz Throughput= function units working as accelerators for the processor. On 39,226clock cycles the other hand, the more special function units are used, the =31.32Mbps. less flexible the processor becomes. As an example, a special function unit dedicated to calculate the backward metric and Theclockcycleneededforasingletrellisstageofthemax- the LLRs could be designed to reduce latency. However, it log-MAP can be calculated as, might be useless for some other functionalities. A common 39,226 Cycle = special function unit to calculate both forward and backward Stage 2×6,144 metric could be better utilized in this case. =3.19cycles. The TTA processor designed here will work for the Viterbi decoding with reasonable throughput. The BRANCH unit for TABLEI the max-log-MAP mode is able to calculate the add-select- NUMBEROFCLOCKCYCLESFORASINGLEITERATION compare operations needed for the Viterbi decoding. Modes Algorithm ClockCycle Acomparisonwithdifferentotherprogrammableimplemen- 1 max-log-MAP 39,226 tations of turbo decoder has been presented in Table III. Our 2 linear-log-MAP 103,436 proposed processor provides very good throughput compared 3 constant-log-MAP 184,454 4 log-MAP 834,253 to most of the programmableimplementations. The processor throughputislowerthantheTTAprocessorof[4]forthesame It can be seen from Table I that the processor takes more clockfrequencyof200MHz,becauseofthecomplexstructure clock cycles if max-log-MAP algorithm is not used. The of QPP interleaver and de-interleaver. Reference Matlab code is available at sites.google.com/site/shahriarshahabuddin/matlab simulator TABLEIII PROGRAMMABLEPROCESSORS [9] A.Nimbalker,Y.W.Blankenship,B.K.Classon,andK.T.Blankenship, “ARP and QPP Interleavers for LTE Turbo coding,” in IEEE Wireless Communications and Networking Conference, pp. 10321037, April Reference Architecture Algorithm Throughput 2008. [13] Motorola max-log-MAP 243Kbps [10] Y. Sun and J. R. Cavallaro, “Efficient hardware implementation of a [12] IntelPentium max-log-MAP 366Kbps highly-parallel 3GPPLTE,LTE-advanceturbodecoder,”inIntegr.,VLSI [14] TMS320C6201DSP max-log-MAP 2Mbps J.,vol.44,no.1,pp.1-11,2010. [15] VLIWASIP max-log-MAP 5Mbps [11] P.Salmela,T.Ja¨rvinenandJ.Takala,“Simplifiedmax-log-MAPdecoder [4] TTAproc.forUMTS max-log-MAP 14.1Mbps structure,” inProceedings ofthe 1st Joint Workshop on Mobile Future Proposed TTAproc. max-log-MAP 31.21Mbps andtheSymposiumonTrendsinCommunications (SympoTIC’06),pp. [4] TTAproc. max-log-MAP 98Mbps 1-11,SanJose,Calif,USA,January2007. [12] M.C.Valenti,J.Sun,“TheUMTSturbocodeandanefficient decoder implementation suitable for software defined radios,” in International Journal on Wireless Information Networks, vol. 8, no. 4, pp. 203-216, VI. CONCLUSION Oct.2001. [13] H. Michel, A. Worm, M. Munch, and N. Wehn, “Hardware software Thepaperdiscussedthedesignissuesofaturbodecoderon trade-offs foradvanced 3Gchannel coding,” inProceedings ofDesign, aTTAprocessor.Thereferenceturbodecoderdesignhasbeen AutomationandTestinEurope,2002. simulatedona Matlablink levelsimulator.Thedesign isthen [14] Y. Song, G. Liu and Huiyang, “The implementation of turbo decoder onDSPinW-CDMAsystem,”inInternational ConferenceonWireless converted and optimized in C language and mapped on the Communications, Networking and Mobile Computing, pp. 1281-1283, TTAprocessorusingTCEtool.Thedesignshowsthepromise Dec.2005. of the possibility of designingseveraldecodingtechniqueson [15] P. Ituero and M. L´opez-Vallejo, “New schemes in clustered VLIW processors applied to turbo decoding,” in Proceedings of International a single TTA processor. As the turbo decoding algorithm is Conference on Application-Specific Systems, Architectures and Pro- very complex, it is very difficult to achieve the LTE target cessors (ASAP ’06), pp. 291-296, Steamboat Springs, Colo, USA, throughput even with pure hardware designs. The parallel September2006. multi-core turbo decoder is the natural choice for the next generationwireless systems. The targetthroughputcould also bereachedbymulti-coreTTAprocessor.Theflexibilitygained from that processor could provide very interesting results and would be a fruitful direction for future research. VII. ACKNOWLEDGEMENT ThisresearchwassupportedbytheFinnishFundingAgency for Technology and Innovation (Tekes), Renesas Mobile Eu- rope,NokiaSiemensNetworks,ElektrobitandXilinx.Special thanksaredueto Dr.PerttuSalmela fromTampereUniversity ofTechnologyforsharinghisinsightsonprogrammableturbo decoder implementations. REFERENCES [1] C. Berrou, A. Glavieux, P. Thitimajshima, “Near shannon limit error- correcting coding and decoding: turbo-codes,” in IEEE International ConferenceonCommunication,vol.2,pp.1064-1070,Geneva,Switzer- land,May1993. [2] Multiplexing andchannel coding, 3GPPTS36.212version10.5.0. [3] P. Ja¨a¨skela¨inen, V. Guzma, A. Cilio, T. Pitka¨nen, and J. Takala, “Codesigntoolsetforapplication-specific instruction-set processors,”in MultimediaonMobileDevices2007,vol.6507ofProceedingsofSPIE pp.1-11,SanJose,Calif, USA,January2007. [4] P.Salmela,H.Sorokin,andJ.Takala,”Aprogrammablemax-log-MAP turbo decoder implementation,” Hindawi VLSI Design, vol. 2008, pp 636-640,2008. [5] S. Benedetto, G. Montorsi, D. Divsalar, and F. Pollara, “A soft-input soft-output maximum a posteriori (MAP) module to decoder parallel and serial concatenated codes,” in JPL TDA Progr. Rep., vol. 42-127, pp.1-20,JetPropulsionLab.,Pasadena, CA,1996. [6] P.Robertson,P.Hoeher,andE.Villebrun,“Optimalandsuboptimalmax- imumaposteriorialgorithmssuitableforturbodecoding,”inEuropean Trans.onTelecommun., vol.8,pp.119-125,Mar./Apr.1997. [7] B. Classon, K. Blankenship, and V. Desai, “Turbo decoding with the constant-log-MAP algorithm,”inProc.,Secondint.Symp.TurboCodes andRelatedAppl.,pp.467-470, Brest,France,Sept.2000. [8] J.-F. Cheng, and T. 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