Design Guide VT82C694X Apollo Pro133A with VT82C686A South Bridge

140 Pages·1999·2.48 MB·English

by  Vanessa Lin

Design Guide
VT82C694X
Apollo Pro133A
with VT82C686A
South Bridge
Preliminary Revision 0.5
November 19, 1999
VIA TECHNOLOGIES, INC.
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REVISION HISTORY
Document Date Revision Initials
Release
0.5 99/91/11 )060RA686&A39 6 dG0nD7a0RB695&X49 6mG oDdrefifid oeMs(ae lleaRitinI , Y,JLV
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5n.o0isi vyerRanimilerP , November 19, 1999 i yrot snioHisiveR
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TABLE OF CONTENTS
Revision History............................................................................................................................................i
Table of Contents..........................................................................................................................................i
List of Figures...............................................................................................................................................i
List of Tables.................................................................................................................................................i
Introduction.................................................................................................................................................1
1.1 About This Design Guide................................................................................................................................1
1.2 Apollo Pro133A Chipset Overview.................................................................................................................2
seruta eeFgdi rhBtr oAN331o roPllo pXA496C 218 .T2V.1 ................................ ................................ ................................ .. 2
seruta etFespi h)CA686C28T Vh(tu orS e2p .u2S.1 ................................ ................................ ................................ ............... 3
marga ikDco lmBet s3 y.S2.1 ................................ ................................ ................................ ................................ ................ 4
1.3 System Design Recommendations...................................................................................................................5
Motherboard Design Guidelines..................................................................................................................7
2.1 Ballout Assignment..........................................................................................................................................7
tnemngis stAuoll aeBgdi rhBtr oAN331o roPl l1o .p1A.2 ................................ ................................ ................................ ...... 7
tnemngis stAuoll aeBgdi rhBtu o"Shtu orSe p2u .S1".2 ................................ ................................ ................................ ......... 8
2.2 Motherboard Description................................................................................................................................9
gnitu od Rntanemeca ldPraobreht o1M- t1o .l2S.2 ................................ ................................ ................................ ................. 9
mets y1S-to lrS orfotc amFr oX1F T.A1.2.2 ................................ ................................ ................................ ................... 10
mets y1S-to lrS orfotc amFr oXF ToAr c2 i.M1.2.2 ................................ ................................ ................................ ......... 11
gnitu od Rntanemeca ldPraobreht o0M73-te k2c .o2S.2 ................................ ................................ ................................ ....... 12
mets y0S73-tekc orS orfotc amFr oX1F T.A2.2.2 ................................ ................................ ................................ ........... 13
mets y0S73-tekc or Sorfotc amFr oX FToA r2c .i2M.2.2 ................................ ................................ ................................ . 14
noitpircs edDra otBiucr idCet n3i .r2P.2 ................................ ................................ ................................ .............................. 15
dra orBeyaL-r u1 o.F3.2.2 ................................ ................................ ................................ ................................ ............... 15
dra orBeyaL- x2 i.S3.2.2 ................................ ................................ ................................ ................................ ................. 16
noitalug erRew odPr a 4o n.BO2.2 ................................ ................................ ................................ ................................ ...... 17
gnilpuoc eeDvitica p5 a.C2.2 ................................ ................................ ................................ ................................ .............. 17
gnilpuoc eeDviticap arCosseco r1P-to leSl g1n .i5S.2.2 ................................ ................................ ................................ ... 18
gnilpuoc eeDviticap arCosseco r0P73-tekc oeSl g2n .i5S.2.2 ................................ ................................ ........................... 19
gnilpuoc eeDviticap atCespi hAC331o roPl l3o .p5A.2.2 ................................ ................................ ................................ . 20
gnilpuoc eeDviticap aeClud o MM4A .R5D.2.2 ................................ ................................ ................................ .............. 20
snoititr aePna lrPe w6 o.P2.2 ................................ ................................ ................................ ................................ .............. 21
draobreht o1M-to lr Sosfnoititr aePna lr Pe1w .o6P.2.2 ................................ ................................ ................................ ... 21
draobreht o0M73-tekc or Sosfnoititr aePna lr Pe2w .o6P.2.2 ................................ ................................ ........................... 23
snoitadnemmoc etRuoy adLnuo rd Gnraew otPes p7i .h2C.2 ................................ ................................ ............................... 25
noitarugifn o pCrUe w8 o.P2.2 ................................ ................................ ................................ ................................ ........... 27
sgnippar tprSUew oXP496C 218 .T8V.2.2 ................................ ................................ ................................ ..................... 28
sgnippar tprSUew oAP686C 228 .T8V.2.2 ................................ ................................ ................................ ..................... 28
2.3 General Layout and Routing Guidelines......................................................................................................29
snoitadnemmoc eeRtubirt teAc a1 r.T3.2 ................................ ................................ ................................ ............................. 29
snoitadnemmoc etRuoy akLco lAC331o roPl l2o .p3A.2 ................................ ................................ ................................ ..... 30
stnemeriuqe Rkco l 1C.2.3.2 ................................ ................................ ................................ ................................ ........... 30
emeh cgSnikc o2 l.C2.3.2 ................................ ................................ ................................ ................................ ............... 31
snoitaredisn ogCnitu okR c3o .l2C.3.2 ................................ ................................ ................................ ............................ 32
snoitanibm okCco lmCet s4 y.S2.3.2 ................................ ................................ ................................ ............................... 33
slang ikSco lMCAR DdS nkaco lUC Pt Cs5 o.H2.3.2 ................................ ................................ ................................ ...... 34
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slang ikSco l6P C.G2A.3.2 ................................ ................................ ................................ ................................ ............. 36
slangi Skcol CIC P7.2.3.2 ................................ ................................ ................................ ................................ .............. 37
slang ikSco lsCuoenalle c8s .i2M.3.2 ................................ ................................ ................................ .............................. 37
noitalucl ahCtgn eeLca rk Tc9o .l2C.3.2 ................................ ................................ ................................ .......................... 38
ygolopo Tdn aselyt Sgnituo R3.3.2 ................................ ................................ ................................ ................................ ..... 40
2.4 VT82C694X Apollo Pro133A Layout and Routing Guidelines....................................................................41
seniledi ugGnitu od Rntauoy aeLcafret nU I Pt1Cs .o4H.2 ................................ ................................ ................................ .. 41
egdi rhBtr ooeNtcafret ntIs o1H- t1o .l1S.4.2 ................................ ................................ ................................ .................. 41
egdi rhBtr ooeNtcafret ntIs o0H73-te k2c .o1S.4.2 ................................ ................................ ................................ .......... 42
egdi rhBtu ooeStcafret ntIs o3U H.P1C.4.2 ................................ ................................ ................................ ................... 44
seniledi ugGnitu od Rntauoy amLetsysb uySr o2m .e4M.2 ................................ ................................ ................................ .. 46
seniledi ugGnitu oMR A1 R.D2.4.2 ................................ ................................ ................................ ................................ 46
tuoy aeLcneref eMR A2 R.D2.4.2 ................................ ................................ ................................ ................................ ... 50
seniledi ugGnitu od Rntauoy aeLcafret n)Ied o X M34P .(G4A.2 ................................ ................................ ........................ 52
snoitadnemmoc egRnitu od Rntauoy alLar e1n .e3G.4.2 ................................ ................................ ................................ .. 52
ed o XMP4 GrA osfcitsiretcara hf Ce2 r.V3.4.2 ................................ ................................ ................................ ............... 53
yrevil erDew oQPD D PV3 G.A3.4.2 ................................ ................................ ................................ .............................. 53
noititr aePna lrPew oQPD D4P V.G3A.4.2 ................................ ................................ ................................ ..................... 55
snoitadnemmoc egRnitu od Rntauoy adLezim i5t .p3O.4.2 ................................ ................................ .............................. 56
seniledi ugGnitu od Rntauoy aeLcafret n4I I.C4P.2 ................................ ................................ ................................ ............ 58
2.5 Super South (VT82C686A) Layout and Routing Guidelines.......................................................................59
rellortn o1B c.S5U.2 ................................ ................................ ................................ ................................ .......................... 59
str oIPDIM/em adG nkan i7L9 ’2 C.A5.2 ................................ ................................ ................................ ............................ 61
kn i7L 91' .C2A.5.2 ................................ ................................ ................................ ................................ ........................ 61
str oIpDIM/e m2 a.G2.5.2 ................................ ................................ ................................ ................................ ............... 62
gnirotin oeMrawd r3 a.H5.2 ................................ ................................ ................................ ................................ ................ 63
rellortn oOrCIep udSetarg e4t .n5I.2 ................................ ................................ ................................ ................................ .. 64
ecafret nsI utBnemegan amMet s5 y.S5.2 ................................ ................................ ................................ ............................ 65
2.5.6 IDE ................................ ................................ ................................ ................................ ................................ ........... 66
MR Do tdnepsu S7.5.2 ................................ ................................ ................................ ................................ ....................... 70
hserf eMRA RdDnep s1 u.S7.5.2 ................................ ................................ ................................ ................................ .... 70
lortn oeCna lrPew oR2P T.S7.5.2 ................................ ................................ ................................ ................................ ... 71
Timing Analysis and Simulation................................................................................................................73
3.1 SDRAM Timing.............................................................................................................................................73
Electrical Specifications.............................................................................................................................75
4.1 Absolute Maximum Ratings..........................................................................................................................75
4.2 Recommended Operating Ranges.................................................................................................................75
4.3 DC Characteristics........................................................................................................................................76
4.4 Power Dissipation..........................................................................................................................................76
Signal Connectivity and Design Checklist..................................................................................................77
5.1 Overview........................................................................................................................................................77
5.2 VT82C694X Apollo Pro133A North Bridge.................................................................................................78
5.3 "Super South" South Bridge Controller.......................................................................................................81
5.4 Apollo Pro-133A Design Checklist................................................................................................................90
tsilkce hsCnoitaredisn otCuoy alLar e1n .e4G.5 ................................ ................................ ................................ .................. 90
tsilkce hsCtnenopm orC o2j .a4M.5 ................................ ................................ ................................ ................................ .... 90
tsilkce hsCnoitadnemmoc egRnilpu o3c .e4D.5 ................................ ................................ ................................ ................... 91
tsilkce heCca rkT c4o .l4C.5 ................................ ................................ ................................ ................................ ............... 92
noitalucla Chtgne Lecar Tkco l 5C.4.5 ................................ ................................ ................................ ................................ 92
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tsilkceh Cetubirtt Aecar Tlang i 6S.4.5 ................................ ................................ ................................ ................................ 94
Appendices.................................................................................................................................................95
Appendix A - SPKR Strapping Application Circuits..........................................................................................97
Appendix B - Audio Codec and Game/MIDI Port Layout Guidelines...............................................................99
noitc u1d.oB rtnI ................................ ................................ ................................ ................................ ................................ 99
snoitadnemmo cte uR2o. yBaL ................................ ................................ ................................ ................................ ......... 100
tnemecal Ptnenopm o 1C.2.B ................................ ................................ ................................ ................................ ........ 100
:senal Prewo Pdn adnuo r 2G.2.B ................................ ................................ ................................ ................................ .. 103
seniledi ugGnit u3 o.R2.B ................................ ................................ ................................ ................................ ............. 105
Appendix C - Apollo Pro133A Reference Design Schematics...........................................................................109
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LIST OF FIGURES
Figure 1-1. Apollo Pro133A System Block Diagram Using the VT82C686A South Bridge............................................................4
Figure 2-1. Major Signal Group Distributions of the Apollo Pro133A Ballout (Top View)............................................................7
Figure 2-2. Major Signal Group Distributions of "Super South" South Bridge Ballout (Top View)................................................8
Figure 2-3. ATX Placement and Routing Example for Slot-1 System...........................................................................................10
Figure 2-4. Micro-ATX Placement and Routing Example for Slot-1 System................................................................................11
Figure 2-5. ATX Placement and Routing Example for Socket-370 System...................................................................................13
Figure 2-6. Micro-ATX Placement and Routing Example for Socket-370 System........................................................................14
Figure 2-7. Four-Layer Stack-up with 2 Signal Layers and 2 Power Planes...............................................................................15
Figure 2-8. Six-Layer Stack-up with 4 Signal Layers and 2 Power Planes..................................................................................16
Figure 2-9. Example of Via Location.........................................................................................................................................17
Figure 2-10. Decoupling Capacitor Placement for Single Slot-1 Processor................................................................................18
Figure 2-11. Decoupling Capacitor Placement for Single Socket-370 Processor........................................................................19
Figure 2-12. Decoupling Capacitor Placements for VT82C694X and VT82C686A.....................................................................20
Figure 2-13. Decoupling Capacitor Placements for DRAM Modules..........................................................................................20
Figure 2-14. ATX Power Plane Partitions for Slot-1 System.......................................................................................................21
Figure 2-15. Micro-ATX Power Plane Partitions for Slot-1 System............................................................................................22
Figure 2-16. ATX Power Plane Partitions for Socket-370 System...............................................................................................23
Figure 2-17. Micro-ATX Power Plane Partitions for Socket-370 System....................................................................................24
Figure 2-18. VT82C694X Power and Ground Layout................................................................................................................25
Figure 2-19. VT82C686A Power and Ground Layout................................................................................................................26
Figure 2-20. A Typical Example of a 3-pin Jumper Strapping Circuit.........................................................................................27
Figure 2-21. System Clock Connections.....................................................................................................................................30
Figure 2-22. Apollo Pro133A Chip Clocking Scheme.................................................................................................................31
Figure 2-23. Clock Trace Spacing Guidelines............................................................................................................................32
Figure 2-24. Effect of Ground Plane to a Clock Signal..............................................................................................................32
Figure 2-25. Series Termination for Multiple Clock Loads.........................................................................................................32
Figure 2-26. Host Clock and SDRAM Clock Layout Recommendations for Slot-1 System...........................................................34
Figure 2-27. Host Clock and SDRAM Clock Layout Recommendations for Socket-370 Systems..................................................35
Figure 2-28. AGP Clock Layout Recommendations....................................................................................................................36
Figure 2-29. PCI Clock Layout Recommendations.....................................................................................................................37
Figure 2-30. Daisy Chain Routing Example...............................................................................................................................40
Figure 2-31. Point-to-Point and Multi-Drop Topology Examples...............................................................................................40
Figure 2-32. Alternate Multi-Drop Topology Example...............................................................................................................40
Figure 2-33. Slot-1 Host Interface Topology Example................................................................................................................41
Figure 2-34. Socket-370 Host Interface Topology Example........................................................................................................42
Figure 2-35. Host Interface Layout Example between Socket-370 and VT82C694X....................................................................43
Figure 2-36. Schematic Example for Slot-1 CPU Internal/External Clock Ratio Pin Sharing.......................................................44
Figure 2-37. Layout Example of Control Signal from South Bridge to Slot-1 CPU......................................................................45
Figure 2-38. Layout Example of Control Signal from South Bridge to Socket-370 CPU..............................................................45
Figure 2-39. Daisy Chain Routing for Four-DRAM DIMM Slots................................................................................................47
Figure 2-40. Daisy Chain Routing for Three-DRAM DIMM Slots..............................................................................................48
Figure 2-41. T-Style Routing for Three-DRAM DIMM Slots.......................................................................................................49
Figure 2-42. Daisy Chain Routing for Two-DRAM DIMM Slots.................................................................................................50
Figure 2-43. DRAM Placement for 133MHz Timing Consideration............................................................................................50
Figure 2-44. Layout Example of Three-DRAM DIMM Slots.......................................................................................................51
Figure 2-45. General Layout Recommendations of AGP 4X Interface........................................................................................52
Figure 2-46. AGP 2X and 4X Mode Sharing Circuit..................................................................................................................53
Figure 2-47. VDDQ Voltage-Switching Application Circuit.......................................................................................................54
Figure 2-48. VDDQ Voltage-Switching Application Circuit (II).................................................................................................54
Figure 2-49. AGP VDDQ Power Plane Partition Example.........................................................................................................55
Figure 2-50. AGP 4X Interface Layout Example.........................................................................................................................57
Figure 2-51. Topology Example of AGP and PCI Interface.........................................................................................................58
Figure 2-52. USB Over-Current Scan Logic..............................................................................................................................59
Figure 2-53. USB Differential Signal Routing Example..............................................................................................................60
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Figure 2-54. AC'97 Link Example..............................................................................................................................................62
Figure 2-55. MIDI/Game Port Application Circuit....................................................................................................................62
Figure 2-56. Hardware Monitoring Application Circuit.............................................................................................................63
Figure 2-57. System Management Bus Interface........................................................................................................................65
Figure 2-58. ISA Bus SA[15:0] / SDD[15:0] Sharing Circuitry..................................................................................................66
Figure 2-59. IDE Interfaces Layout Guidelines..........................................................................................................................67
Figure 2-60. Ultra DMA/66 Placement and Routing Example....................................................................................................68
Figure 2-61. Ultra DMA/66 Application Circuit.........................................................................................................................69
Figure 2-62. Suspend DRAM Refresh Application Circuit..........................................................................................................70
Figure 2-63. STR State Power Plane Control Application Circuit..............................................................................................71
Figure 3-1. CPU Read from SDRAM (SL=2).............................................................................................................................73
Figure 3-2. CPU Post Write to SDRAM (SL=2).........................................................................................................................74
Figure A-1. VT82C686A SPKR Pin Transistor Driver Solution (I).............................................................................................97
Figure A-2. VT82C686A SPKR Pin Inverter Driver Solution (II)................................................................................................97
Figure B-1. AC’97 Audio Codec and Game/MIDI Port Block Diagram......................................................................................99
Figure B-2. AC’97 Audio Codec and GAME/MIDI Port Placement Example...........................................................................100
Figure B-3. Ground Layer Layout Example.............................................................................................................................103
Figure B-4. Power Layer Layout Example...............................................................................................................................104
Figure B-5. Component Layer Layout Example.......................................................................................................................106
Figure B-6. Solder Layer Layout Example...............................................................................................................................106
Figure C-1. Apollo Pro133A Reference Component Placement................................................................................................110
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LIST OF TABLES
Table 2-1. Different Board Size Lists for Slot-1 System................................................................................................................9
Table 2-2. Different Board Size Lists for Socket-370 System.......................................................................................................12
Table 2-3. High Frequency and Bulk Decoupling Capacitor Distribution around Socket-370.....................................................19
Table 2-4. Power-Up Configuration for VT82C694X.................................................................................................................28
Table 2-5. Power-Up Configuration for VT82C686A.................................................................................................................28
Table 2-6. Recommended Trace Width and Spacing...................................................................................................................29
Table 2-7. Apollo Pro133A Clock Synthesizer Requirements......................................................................................................30
Table 2-8. Apollo Pro133A System Clock Combinations............................................................................................................33
Table 2-9. Host Control Signals to South Bridge........................................................................................................................44
Table 2-10. Memory Subsystem Signals.....................................................................................................................................46
Table 2-11. VT82C694X AGP 4X Signal Groups.......................................................................................................................52
Table 2-12 Universal Serial Bus (USB) Signals.........................................................................................................................59
Table 2-13. Signal Description of AC'97 Link and Game/MIDI Ports.........................................................................................61
Table 2-14. Resume Events Supported in Different Power States................................................................................................71
Table 4-1. Absolute Maximum Ratings.......................................................................................................................................75
Table 4-2. Recommended Operating Ranges..............................................................................................................................75
Table 4-3. DC Characteristics...................................................................................................................................................76
Table 4-4. Maximum Power Dissipation....................................................................................................................................76
Table 5-1. VT82C694X North Bridge Connectivity.....................................................................................................................78
Table 5-2. VT82C686A South Bridge Connectivity.....................................................................................................................81
Table 5-3. Recommended Trace Width and Spacing...................................................................................................................90
Table 5-4. Maximum Accumulated Trace Length.......................................................................................................................94
Table B-1. Decoupling Capacitor List.....................................................................................................................................101
Table B-2. AC-Coupling Capacitors for Audio Input Signals....................................................................................................101
Table B-3. AC-Coupling Capacitors for Audio Input Signals....................................................................................................102
Table B-4. Signal Groups Associated with Their Audio Ground Plane......................................................................................104
Table B-5. Routing Guidelines for Signal Nets.........................................................................................................................107
Table B-6. Routing Guidelines for Power and Ground Nets.....................................................................................................107
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