Table Of ContentStéphane Badel · Can Baltaci
Alessandro Cevrero · Yusuf Leblebici
Design Automation
for Diff erential MOS
Current-Mode Logic
Circuits
Design Automation for Differential MOS
Current-Mode Logic Circuits
Stéphane Badel (cid:129) Can Baltaci (cid:129) Alessandro Cevrero
Yusuf Leblebici
Design Automation for
Differential MOS
Current-Mode Logic Circuits
123
StéphaneBadel CanBaltaci
ÉcolePolytechniqueFédéraledeLausanne ÉcolePolytechniqueFédéraledeLausanne
Lausanne,Switzerland Lausanne,Switzerland
AlessandroCevrero YusufLeblebici
IBMResearch–Zurich ÉcolePolytechniqueFédéraledeLausanne
Rüschlikon,Switzerland Lausanne,Switzerland
ISBN978-3-319-91306-3 ISBN978-3-319-91307-0 (eBook)
https://doi.org/10.1007/978-3-319-91307-0
LibraryofCongressControlNumber:2018941809
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Preface
Our detailed research work on the design and optimization of high-performance
MOS current mode logic (MCML) circuits at the Microelectronic Systems Lab-
oratory (LSM) of EPFL started more than a decade ago. In the beginning, our
main motivation was the reduction of power supply noise and substrate noise
generated by high-speed logic units that have to operate in very close proximity
to sensitive analog building blocks. While the fundamental concepts used in the
design of MCML circuits were fairly well understood, relatively little work was
availableatthattimetoguidesystematicanalysisandespeciallydesignautomation
of such circuits. Our early research in this domain has led to the development
of differential logic cell optimization techniques under arbitrary load conditions,
as well as fully differential logic synthesis, and placement-and-routing (P&R)
strategies that enable straightforward design automation of logic functions based
onconventionalhardwaredescriptionlanguagessuchasVHDLandVerilog.Such
logic units distinguish themselves with their capability of operating at multi-GHz
frequencies while producing extremely low levels of supply noise. Nowadays,
MCML-based circuit solutions are commonly used in various applications where
high-performanceoperationistheprimaryobjective.
In addition to high-speed operation, the fully differential nature of the MCML
circuit style lends itself to implementation of logic blocks in which the power
supplysignatureassociatedwiththelogicoperationscanbeeffectivelysuppressed.
This property results in highly efficient implementation of various cryptographic
functionswitharemarkableimmunitytodifferentialpoweranalysis(DPA)attacks.
The fully differential current-mode operation principle of MCML circuits has
also paved the way for the development of a completely new class of ultralow-
powerlogiccircuitscalledsub-thresholdsource-coupledlogic(ST-SCL)whichcan
achieve impressive energy efficiency operating with very low tail current levels
(downtoafewpA)whileproducingseveralhundredsofmVoutputvoltageswing—
afeaturethatissimplynotpossibleinconventionalCMOSlogiccircuitsoperating
insub-thresholdregime.Ourextensiveworkinthisparticulardirectionhasalready
v
vi Preface
been published in the form of a separate volume from Springer, entitled Extreme
Low-Power Mixed Signal IC Design coauthored by A. Tajalli and Y. Leblebici
(ISBN978-1-4419-6477-9).
This volume covers systematic, in-depth analysis of MCML circuits in Part I
(Chaps. 2 and 3), followed by the principles of design automation for MCML
in Part II (Chaps. 4 and 5), addressing fully differential logic synthesis, standard
cell design, pin assignment, and placement-and-routing strategies. The last four
chapters (Part III) of the book are dedicated to specific design examples for high-
speeddesignaswellascryptographiccircuitapplications,suchastheDPA-resistant
implementationsofGrain-128streamcipherandAESengines.Thetopicscovered
in this book would be beneficial to graduate students specializing in high-speed
circuit design, as well as engineering professionals designing systems for high
performanceandDPAimmunity.
Theauthorsaretrulyindebtedtomanyindividualswhohavecontributedtothis
work. Our graduate students, as well as our colleagues, have consistently helped
us with their generous assistance along the way. In particular, we acknowledge
the valuable support provided over the years by Dr. Ilhan Hatirnaz, Dr. Francesco
Regazzoni, Dr. Armin Tajalli, Ms. Tugba Demirci, and Mr. Michael Schwander.
Thisworkwouldnothavebeenpossiblewithouttheircontributions.
Lausanne,Switzerland StéphaneBadel
Lausanne,Switzerland CanBaltaci
Rüschlikon,Switzerland AlessandroCevrero
Lausanne,Switzerland YusufLeblebici
14May2018
Contents
1 Introduction................................................................. 1
1.1 NoiseinIntegratedCircuits.......................................... 1
1.2 Low-NoiseCMOSLogicFamilies.................................. 2
1.3 MOSCurrent-ModeLogic........................................... 3
1.4 OrganizationoftheBook ............................................ 3
References.................................................................... 3
PartI AnalysisandDesignofMOSCurrent-ModeLogicCircuits
2 AnalysisofMOSCurrent-ModeLogicCircuits ........................ 7
2.1 TheEKVMOSFETTransistorModel .............................. 7
2.1.1 StrongInversionRegime .................................... 7
2.1.2 WeakInversionRegime...................................... 8
2.1.3 ModerateInversionRegime................................. 8
2.2 TheMOSDifferentialPair........................................... 9
2.2.1 StrongInversionOperation.................................. 9
2.2.2 SubthresholdOperation...................................... 12
2.2.3 TransregionalModel......................................... 13
2.3 Single-LevelMCMLLogicGate.................................... 16
2.3.1 ImplementationofLoadDevices............................ 17
2.3.2 DCTransferCharacteristic.................................. 18
2.3.3 NoiseMargin................................................. 19
2.3.4 LogicLevels.................................................. 24
2.3.5 DynamicOperation.......................................... 26
2.4 Multi-LevelMCMLLogicGates.................................... 30
2.4.1 DCOperation ................................................ 32
2.4.2 Common-ModeInputLevelandLevelShifting............ 35
2.4.3 DynamicOperation.......................................... 38
2.5 EffectofNonlinearities .............................................. 39
2.5.1 LoadDevices................................................. 40
2.5.2 DifferentialPairs............................................. 44
vii
viii Contents
2.5.3 JunctionCapacitances ....................................... 45
2.5.4 OverallNoisePerformance.................................. 46
2.6 RandomEffects ...................................................... 47
2.6.1 ProcessVariations............................................ 48
2.6.2 On-ChipVariationsandMismatch.......................... 49
2.6.3 NumericalExample.......................................... 55
References.................................................................... 57
3 DesignofMOSCurrent-ModeLogicCells.............................. 59
3.1 DesignMethodologyforMCMLLogicGates...................... 59
3.1.1 Trade-Offs.................................................... 59
3.1.2 PracticalLimitsoftheVoltageSwing ...................... 62
3.2 MCMLLatchesandFlip-Flops...................................... 64
3.2.1 MCMLMemoryElement ................................... 64
3.2.2 MCMLLatch................................................. 65
3.2.3 Master–SlaveMCMLLatch................................. 68
3.2.4 MCMLFlip-Flop ............................................ 70
3.2.5 DualEdge-TriggeredElements.............................. 74
3.3 Tri-StateMCMLBuffers............................................. 75
3.4 High-SpeedandLow-PowerTechniques............................ 78
3.4.1 SpeedEnhancementwithPeakingTechniques............. 78
3.4.2 Triple-RailMCML........................................... 84
References.................................................................... 87
PartII DesignAutomationforDifferentialCircuits
4 DesignMethodologyforMCMLStandardCells ....................... 91
4.1 StandardCellsandSemi-customDesign............................ 91
4.1.1 Semi-customFlowOverview................................ 91
4.1.2 StandardCells................................................ 92
4.2 LogicGatesSynthesis................................................ 95
4.2.1 BinaryDecisionDiagrams................................... 95
4.2.2 AnalysisofBDDsandMCMLNetworks .................. 97
4.2.3 SynthesisofBDDsandMCMLNetworks.................. 98
4.2.4 ReductionofBDDs.......................................... 98
4.2.5 VariableOrderingandOptimumImplementation.......... 100
4.2.6 Multi-StageDecomposition ................................. 103
4.3 TemplateApproachforMCMLStandard-CellLibrary ............ 104
4.3.1 MCMLFootprints............................................ 105
4.3.2 ClassificationofBooleanFunctions ........................ 106
4.3.3 MCMLTemplates............................................ 108
4.3.4 ProposedSetofStandardCells.............................. 110
4.3.5 AutomaticTemplateGeneration ............................ 112
4.4 Standard-CellDesign ................................................ 113
4.4.1 DesignParameters ........................................... 113
Contents ix
4.4.2 CellLayout................................................... 114
4.4.3 UnitCellSizing.............................................. 116
References.................................................................... 116
5 DesignAutomationforDifferentialCircuits............................. 117
5.1 Overview.............................................................. 117
5.2 LogicSynthesis....................................................... 119
5.2.1 SynthesiswithDifferentialCells............................ 119
5.2.2 Bias Generator and Level Converters in the
SynthesisProcess ............................................ 121
5.3 PlacementandRouting............................................... 122
5.3.1 RoutingofDifferentialNets................................. 124
5.3.2 VariantCellsinthePlaceandRouteFlow.................. 127
5.3.3 ParasiticsModeling.......................................... 127
PartIII DesignExamples
6 DesignExampleI:Low-NoiseEncoderCircuitforA/DConverter... 133
6.1 CircuitDescription................................................... 133
6.2 MCMLCellLibrary.................................................. 133
6.2.1 LibraryParameters........................................... 134
6.2.2 CellSelection ................................................ 135
6.2.3 CellCharacteristics .......................................... 135
6.2.4 CellLayout................................................... 137
6.2.5 BiasGenerator ............................................... 137
6.2.6 LevelConverters............................................. 137
6.3 DesignFlow .......................................................... 138
6.4 Results ................................................................ 141
6.4.1 EncoderRedesign............................................ 141
6.4.2 ArchitectureModification ................................... 145
6.4.3 DesignFlow.................................................. 146
Reference..................................................................... 149
7 DesignExampleII:High-SpeedMultiplexer............................ 151
7.1 CircuitDescription................................................... 151
7.2 MCMLCellLibrary.................................................. 151
7.2.1 LibraryParameters........................................... 153
7.2.2 CellSelection ................................................ 154
7.2.3 CellCharacteristics .......................................... 154
7.3 ImplementationResults.............................................. 155
8 DesignExampleIII:Grain-128aStreamCipher ....................... 157
8.1 MCMLforCryptographicApplications ............................ 157
8.2 CircuitDescription................................................... 158
8.2.1 Authentication................................................ 160
8.2.2 KeyStreamGeneration...................................... 161
8.2.3 OutputRate................................................... 161
x Contents
8.3 MCMLCellLibrary.................................................. 161
8.3.1 LibraryParameters........................................... 161
8.3.2 CellSelection ................................................ 161
8.3.3 CellCharacteristics .......................................... 162
8.3.4 CellLayout................................................... 164
8.4 ImplementationResults.............................................. 164
8.4.1 ComparisonofMCMLandCMOS......................... 164
References.................................................................... 170
9 DesignExampleIV:AdvancedEncryptionStandard(AES).......... 171
9.1 CircuitDescription................................................... 171
9.2 MCMLCellLibrary.................................................. 172
9.2.1 StandardCellDesignwithPowerGating................... 172
9.2.2 CellSelection ................................................ 174
9.2.3 CellCharacteristics .......................................... 174
9.3 ImplementationResults.............................................. 177
References.................................................................... 180
10 Conclusions.................................................................. 181
10.1 FutureWork .......................................................... 182
Appendix A Large-Signal Transitional Model of the MOS
DifferentialPair............................................................. 183
AppendixB ListofMCMLTemplatesuptoThreeLevels................ 187
FurtherReading.................................................................. 227
Index............................................................................... 229
