Design and Test of Integrated Inductors for RF Applications

202 Pages·2004·14.119 MB·English

by  Jaime Aguilera, Roc Berenguer (auth.)

DESIGN AND TEST OF INTEGRATED INDUCTORS
FOR RF APPLICATIONS
Design and Test
of Integrated Inductors
for RF Applications
by
Jaime Aguilera
Vision Technologies,
Spain
and
Roc Berenguer
Centro de Estudios e Investigaciones Técnicas de Gipuzkoa (C.E.I.T.),
Spain
KLUWER ACADEMIC PUBLISHERS
NEW YORK,BOSTON, DORDRECHT, LONDON, MOSCOW
eBookISBN: 0-306-48705-5
Print ISBN: 1-4020-7676-2
©2004 Kluwer Academic Publishers
NewYork, Boston, Dordrecht, London, Moscow
Print ©2003 Kluwer Academic Publishers
Dordrecht
All rights reserved
No part of this eBook maybe reproducedor transmitted inanyform or byanymeans,electronic,
mechanical, recording, or otherwise, without written consent from the Publisher
Created in the United States of America
Visit Kluwer Online at: http://kluweronline.com
and Kluwer's eBookstoreat: http://ebooks.kluweronline.com
Dedication
This book is dedicated to my
parents Juan and Mari, and to
my girlfriend Marta.
Jaime Aguilera
This book is dedicated to my
parents Laureà and Rosa, and
to my brothers and sisters.
Roc Berenguer
Contents
Dedication v
Contents vii
List of Figures xi
List of Tables xvii
List of Abbreviations xix
Preface xxi
1. Introduction 1
1. Conventional IC fabrication technologies 4
2. Keys to progress in RF transceiver design; High Q integratedinductors 8
2.1 LC Parallel Tank 9
2.1.1 Low Noise Amplifiers (LNA) 11
2.1.2 VoltageControlledOscillators(VCO) 14
2.2 Inductive degeneration for matching purposes 16
2.3 RF Filters 18
3. The challenge of integrating high quality inductors 19
3.1 Metal losses 20
3.2 Substrate losses 21
4. Structure of the book 21
viii Design and test of integrated inductors for RF applications
2. General considerations 23
1. Ways of integrating an inductor 23
1.1 Conventional fabrication processes 24
1.2 Non-conventional fabrication processes 27
2. Spiral inductors on silicon based technologies 28
2.1 Physical overview: Difficulty of integrating an inductor 29
2.1.1 Inductance 30
2.1.1.1 Self inductance 30
2.1.1.2 Mutual inductance 31
2.1.1.3 Total inductance 34
2.1.2 Resistance 35
2.1.2.1 Skin effect 36
2.1.2.2 Proximity effects 37
2.1.3 Parasitic effects in the substrate 37
2.1.3.1 Magnetically induced parasitic effects in the substrate 38
2.1.3.2 Electrically induced parasitic effects in the substrate 38
2.1.4 Parasitic capacitance between metal turns 40
2.2 Spiral inductor electrical models 41
2.2.1 model 41
2.2.2 Transformermodel 44
2.2.3 Wideband model 45
2.3 Quality factor definition 47
2.3.1 definition 48
2.3.2 definition 48
2.3.3 definition 49
2.4 Different attempts to predict the performance 50
2.4.1 Field electromagnetic simulators 51
2.4.2 ASITIC 51
2.4.3 Method based in the model parameter definition 51
2.5 Quality factor improvement methods 53
2.5.1 Broken guard ring 54
2.5.2 Biased N-well beneath the inductor 56
2.5.3 Substrate shielding 58
2.5.4 Non conventional fabrication processes 60
3. Inductor’s test and characterization 63
1. On wafer measuring equipment 66
1.1 Vector Network Analyzer 66
1.2 Probes 68
1.3 Probe station 73
1.4 Commercial calibration kits 75
2. Measuring accuracy and Repeatability 76
2.1 Different types of measuring errors 76
Design and test of integrated inductors for RF applications ix
2.2 Random errors 77
2.3 Systematic errors 77
2.3.1 Systematic errors due to VNA 78
2.3.2 Cables and connectors 79
2.3.3 Probes 80
2.4 Calibration 80
2.4.1 SOLT Calibration 82
2.5 Repeatability and accuracy 85
3. Measuring configuration: 1-port versus 2-port configuration 87
3.1 General Case 88
3.1.1 Two-Port measurement with the device placed in series 89
3.1.2 Two-Port measurement with the deviceplaced in parallel 89
3.1.3 One-Port measurement 90
3.2 Inductor model case 91
3.2.1 Two-Port measurement with the model placed in series 92
3.2.2 Two-Port measurement with the model placed in parallel 93
3.2.3 One-Port measurement 95
3.3 Sensitivity analysis 96
4. Test fixture design 102
4.1 Substrate related issues 104
4.1.1 Interterminal coupling 105
4.1.2 Interport coupling 109
4.2 Metallization related issues 113
4.2.1 Pad material 113
4.2.2 Probe tip material 114
4.2.3 Probe alignment 114
4.2.4 Setup stability 115
4.2.5 Tolerances 115
4.2.6 Wear of the probes and the pads 115
4.3 General Guidelines 116
5. De-embedding techniques 118
5.1 Test-fixture model 118
5.2 In-fixture standards 120
5.3 De-embedding procedure 121
6. model inductor characterization 127
4. Influence of the geometric parameters on the inductor’s performance:
Design rules 135
1. Problem description 135
2. Analytical study and simulations 137
2.1 Number of sides 137
2.2 Spacing between tracks 139
2.3 External radius and number of turns 141
x Design and test of integrated inductors for RF applications
2.3.1 Number of turns 141
2.3.2 External radius 142
2.4 Width 143
2.5 Metal layers connected in parallel 145
3. Empirical study 148
3.1 Inductor selection 148
3.2 Fabrication and measurement 149
3.3 Analysis of the empirical data 150
3.3.1 External radius and number of turns 152
3.3.1.1 Influence of the proximity effect on the internal turns 153
3.3.1.2 Link between the track width and proximity effect 156
3.3.2 Skin and corner effects 158
3.3.3 Geometry of the via 160
3.3.4 Trackwidth higher than 162
4. Design considerations 163
5. Inductor’s design flow 165
1. Generation phase 167
2. Filtering phase 168
2.1 Inductance filtering 168
2.2 CM and internal radius 168
3. Performance estimation phase 169
4. Verification phase 170
Appendix 173
References 177
Index 185
List of Figures
Figure 1-1. Weight and size improvement experimented by mobile phones from
year 1993 to 2001. 2
Figure 1-2. a)Super heterodyne and b) Low IF radio architectures. 3
Figure 1-3. RF Technologies: a)GaAs MESFET b) GasAs HBT c) Advanced
Si-Bipolar d) SiGe HBT e) CMOS 7
Figure 1-4. Parallel LC tank circuit. 9
Figure 1-5. Realistic model for a parallel LC tank. 10
Figure 1-6. Narrow-band differential low noiseamplifier topology. 12
Figure 1-7. Simplified smallsignal equivalent circuit. 13
Figure 1-8. Different VCO topologies depending on implemented feedback. 14
Figure 1-9. Basic LC-tuned oscillator. 15
Figure 1-10. LNA input with inductive degeneration. 17
Figure 1-11. Small signal equivalent circuit of the input of the LNA of Figure 1-10.
18
Figure 1-12. LC Low-pass filter. 19
Figure 1-13. Loss mechanisms. 20
Figure 2-1. Microphotography of a squared, octagonal, and icosagonal inductor
with a CMOS technology. 24
Figure 2-2. Microphotography of a voltage controlled oscillator using two spirals
fabricated with a CMOS technology in a mirror configuration.
25
Figure 2-3. Microphotography of a balanced inductor fabricated on a
SiGe. 25
Figure 2-4. Geometry of a centre-tapped inductor. 26
Figure 2-5. Diagram of a multilevel inductorusing two metal layers. 26
Figure 2-6. Multilevel geometry for maximizing the inductance per unite area. 27
xii Design and test of integrated inductors for RF applications
Figure 2- 7. Microphotography of: a) toroidal inductor b) solenoidal inductor with
inclined top and bottom conductor [Ahn98] and c) solenoidal inductor
with parallel conductor [Yoon99]. 28
Figure 2-8. Cross-section of an integrated spiral inductor on a Si technology and
the physical effects that arise when a time-varying voltage is applied
across its ends. 29
Figure 2-9. Self inductance value for a rectangular conductor versus its length and
width (the thickness is fixed at 31
Figure 2-10. Method for computing the GMD betweenareas. 32
Figure 2-11. Mutual inductance of two rectangular conductors versus distance
between centres and width. 33
Figure 2-12. Mutual inductance of two rectangular conductors versus width and
separation between them. 33
Figure 2-13. Illustration of the positive and negative mutual inductance of a
squared planar spiral. 35
Figure 2-14. Illustration of the skin effect in a rectangular conductor. 36
Figure 2-15. Schematic representation of the induced currents in the substrate due
to the magnetic field penetration. 38
Figure 2-16. Schematic representation of the metal-substrate capacitance. 39
Figure 2-17. Schematic representation of the displacement currents due to the
metal-substrate capacitance. 40
Figure 2-18. Schematic representation of the parasitic capacitance between layers
and metal tracks. 41
Figure 2-19. Two-port model. 42
Figure 2-20. One-port model. 44
Figure 2-21. Transformer Model. 45
Figure 2-22. Wideband model. 46
Figure 2-23. Simplified model. 49
Figure 2-24. Equivalent energetic model for the one-port model. 52
Figure 2-25. Schematic view of a spiral with a brokenguard ring. 54
Figure 2-26. One-port model of a spiral with a broken guard ring. 55
Figure 2-27. Schematicview of an inductor with a biased N-well beneath it. 56
Figure 2-28. One-port model of an inductor with a biased N-well beneaththe
inductor. 57
Figure 2-29. One port model of a spiralwith substrateshielding. 58
Figure 2-30. View of a squared spiral with a patterned ground shield underneath
the spiral. 59
Figure 2-31. Microphotography of an inductor without substrate underneath the
spiral [Chan98]. 61
Figure 3-1. Individual die mounted on a test fixture. 63
Figure 3-2. Basic elements involved in the characterization of a passive element.
64