Design and Realization of a Single Stage Sigma-Delta ADC With Low Oversampling Ratio PDF
Preview Design and Realization of a Single Stage Sigma-Delta ADC With Low Oversampling Ratio
BBrriigghhaamm YYoouunngg UUnniivveerrssiittyy BBYYUU SScchhoollaarrssAArrcchhiivvee Theses and Dissertations 2006-09-28 DDeessiiggnn aanndd RReeaalliizzaattiioonn ooff aa SSiinnggllee SSttaaggee SSiiggmmaa--DDeellttaa AADDCC WWiitthh LLooww OOvveerrssaammpplliinngg RRaattiioo Yongjie Cheng Brigham Young University - Provo Follow this and additional works at: https://scholarsarchive.byu.edu/etd Part of the Electrical and Computer Engineering Commons BBYYUU SScchhoollaarrssAArrcchhiivvee CCiittaattiioonn Cheng, Yongjie, "Design and Realization of a Single Stage Sigma-Delta ADC With Low Oversampling Ratio" (2006). Theses and Dissertations. 796. https://scholarsarchive.byu.edu/etd/796 This Dissertation is brought to you for free and open access by BYU ScholarsArchive. It has been accepted for inclusion in Theses and Dissertations by an authorized administrator of BYU ScholarsArchive. For more information, please contact [email protected], [email protected]. DESIGN AND REALIZATION OF A SINGLE STAGE SIGMA-DELTA ADC WITH LOW OVERSAMPLING RATIO by Yongjie Cheng A dissertation submitted to the faculty of Brigham Young University in partial fulfillment of the requirements for the degree of Doctor of Philosophy Department of Electrical and Computer Engineering Brigham Young University December 2006 BRIGHAM YOUNG UNIVERSITY GRADUATE COMMITTEE APPROVAL of a dissertation submitted by Yongjie Cheng This dissertation has been read by each member of the following graduate committee and by majority vote has been found to be satisfactory. Date David J. Comer, Chair Date Donald T. Comer Date Michael D. Rice Date Doran K. Wilde Date Richard H. Selfridge BRIGHAM YOUNG UNIVERSITY As chair of the candidate’s graduate committee, I have read the dissertation of Yongjie Cheng in its final form and have found that (1) its format, citations, and bibliographical style are consistent and acceptable and fulfill university and department style requirements; (2) its illustrative materials including figures, tables, and charts are in place; and (3) the final manuscript is satisfactory to the graduate committee and is ready for submission to the university library. Date David J. Comer Advisor Chair, Graduate Committee Accepted for the Department Michael J. Wirthlin Graduate Coordinator Accepted for the College Alan R. Parkinson Dean, Ira A. Fulton College of Engineering and Technology ABSTRACT DESIGN AND REALIZATION OF A SINGLE STAGE SIGMA-DELTA ADC WITH LOW OVERSAMPLING RATIO Yongjie Cheng Department of Electrical Engineering Doctor of Philosophy Due to the rapid growth of the communication market, a large amount of research is in process toward a high speed and high resolution sigma-delta A/D converter. This dissertation focuses on the design of a single-stage sigma-delta A/D converter with very low oversampling ratio for the wireless application. An architecture for a multibit single- stage delta-sigma A/D converter with two-step quantization is proposed. Both the MSB and LSB signals produced by the two-step quantization are fed back simultaneously to all integrator stages, making it suitable for low oversampling ratios. The two-step ADC avoids the problem that the complexity of an internal flash ADC increases exponentially with each added bit. A segmented architecture with coarse/fine DEM and DAC is proposed to reduce the complexity of DEM and DAC due to the large internal quantizer. The consequence of the segmentation, mismatch between coarse and fine DACs can be noise-shaped by using a digital requantization (REQ) algorithm. A second-order single- stage sigma-delta A/D converter with 8-bit two-step inner quantization is proposed in this dissertation, which employs the feed-forward branches to reduce the integrator output swing. The proposed modulator is implemented with TSMC 0.25 μm mixed-signal process, using the switched-capacitor circuit. The measured system achieves the dynamic range of 70 dB under an oversampling ratio of 16 with the REQ algorithm reducing the noise floor in the signal bandwidth by 20 dB.
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