Design and Optimization of Low-power Level-crossing ADCs

148 Pages·2012·8.42 MB·English

Design and Optimization of Low-power
Level-crossing ADCs
Colin Weltin-Wu
Submitted in partial fulfillment of the
requirements for the degree of
Doctor of Philosophy
in the Graduate School of Arts and Sciences
COLUMBIA UNIVERSITY
2012
©2012
ColinWeltin-Wu
AllRightsReserved
Abstract
Mixed-Signal Circuit Techniques
for Low Power and High Speed
Level Crossing ADCs
Colin Weltin-Wu
This thesis investigates some of the practical issues related to the implementation of level-
crossingADCsinnanometerCMOS.Alevel-crossingADCtargetingminimumpowerisdesigned
and measured. Three techniques to circumvent performance limitations due to the zero-crossing
detectorattheheartoftheADCareproposedanddemonstrated: anadaptiveresolutionalgorithm,
an adaptive bias current algorithm, and automatic offset cancelation. The ADC, fabricated in 130
nm CMOS, is designed to operate over a 20 kHz bandwidth while consuming a maximum of 8.5
µW. A peak SNDR of 54 dB for this 8-bit ADC demonstrates a key advantage of level-crossing
sampling,namelySNDRhigherthantheclassicNyquistlimit.
Contents
ListofFigures iii
ListofTables x
1 Level-CrossingSamplingSystems 1
1.1 ThesisOutlineandGoals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2 ConsiderationsforLowPower 8
2.1 TopologyandSpecification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2 FeedbackDAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.3 ZeroCrossingDetectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.4 DigitalLogic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.4.1 InterconnectCapacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3 DelayDistortionandNoiseAnalysis 25
3.1 Input-DependentZCDDelay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
i
3.1.1 AModelForZCDDelay . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.1.2 HarmonicDistortionofaLevelCrossingQuantizer . . . . . . . . . . . . . 33
3.1.3 Delay-Dispersion-InducedHarmonicDistortion . . . . . . . . . . . . . . . 39
3.2 NoiseAnalysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.2.1 ZCDNoise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4 DesignofaµWProgrammableLCADC 55
4.1 AdaptiveResolutionAlgorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
4.2 ProgrammableAsynchronousTimingGeneration . . . . . . . . . . . . . . . . . . 66
4.3 ZeroCrossingDetectorswithDynamicCurrentBias . . . . . . . . . . . . . . . . 69
4.3.1 Three-StageZeroCrossingDetector . . . . . . . . . . . . . . . . . . . . . 69
4.3.2 CurrentBiasDACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
4.4 SegmentedCapacitorFeedbackDAC . . . . . . . . . . . . . . . . . . . . . . . . . 76
4.5 AutomaticOffsetCalibrationwithOscillator . . . . . . . . . . . . . . . . . . . . . 81
4.5.1 RelaxationOscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
4.6 OtherCircuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
4.6.1 BootstrappedInputSwitch . . . . . . . . . . . . . . . . . . . . . . . . . . 85
4.6.2 Current-SteeringReconstructionDAC . . . . . . . . . . . . . . . . . . . . 87
4.6.3 AsynchronousController . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
4.6.4 SPIandCalibrationLogic . . . . . . . . . . . . . . . . . . . . . . . . . . 89
5 LCADCMeasurements 90
ii
5.1 Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
5.2 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
5.3 LCADCSystemPerformance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
5.4 CalibrationAlgorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
5.5 DelayElements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
5.6 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
6 ConclusionsandSuggestionsforFutureWork 113
6.1 PerformanceComparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
6.1.1 Level-CrossingADCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
6.1.2 SynchronousADCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
6.2 SuggestionsforFutureWork . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
A DerivationofDistortionEquations 123
A.1 TheFourierComponentsc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
m,n
A.2 Non-UniformDelayImpactonHarmonicDistortion . . . . . . . . . . . . . . . . 125
A.3 InputSlopeatTR (t)Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . 127
m
B SiliconErrata 129
iii
List of Figures
1.1 A2-bit(4-level)level-crossingsampler,withuniformquantizationlevels. . . . . . 2
2.1 AsimpleLCADCimplementedasaflash. . . . . . . . . . . . . . . . . . . . . . . 9
2.2 Transfercharacteristicofan(a)mid-riseand(b)mid-treadquantizeraround0. . . . 10
2.3 The digital output x (t) of the LCADC contains the information of the samples,
q
shown as the circles in the graph. The continuous-time DAC generates a zero-
order-held-likereconstructionoftheanaloginputfromthesamples. . . . . . . . . 11
2.4 FeedbackLCADCtopology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.5 Feedback LCADC topology with a capacitive DAC. The capacitive DAC recon-
structs v (t) as before, and subtracts it from v (t) capacitively so that the ZCD
xq x
inputrangeisreduced. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.6 Schematic of the capacitive DAC, using a classic charge-redistribution array. The
operationofthedacRST anddacEN signalswillbeexplainedshortly. . . . . . . . 16
iv
2.7 Timing diagram of the control signals for the capacitive DAC. The ZCD signal
referstothevaryingZCDinput,eitherV+fortheupperZCDorV−forthelower
ZCD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.8 Differentconfigurationsofabinarybus. . . . . . . . . . . . . . . . . . . . . . . . 22
3.1 AZCDstagemodeledwithasaturatingtransconductorandsingleoutputpole. . . . 26
3.2 On the left, the ZCD input can be approximated as a series of voltage ramps. The
dashed horizontal grey lines indicate the input range of the ZCD where the output
is not saturated. On the right, the actual ZCD response is superimposed over an
idealresponseingrey. TheactualZCDzerocrossingattimet isdelayedfromthe
c
ideal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.3 Reducing bandwidth and increasing gain proportionally cause the first-order sys-
temtobehavemoreandmorelikeanidealintegrator. . . . . . . . . . . . . . . . . 30
3.4 Delayvs. inputslope,andthetwoapproximationsin(3.5)and(3.12). . . . . . . . 31
3.5 Delay of a three stage cascaded amplifier, by stage. Also shown is the delay of
singlestagethathasthesameoverallgainandbandwidthasthecascade. . . . . . . 32
3.6 With symmetric quantization levels, it is possible to express the quantized signal
with2N−1 signalsTR (t). Foranodd-symmetricinput,eachoftheTR (t)signals
m m
isalsooddsymmetric. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.7 TheFourierseriesapproximationofv (t)foranalmostfull-scaletime-normalized
xq
sinusoidinput,for150,800,and4000Fourierterms. . . . . . . . . . . . . . . . . 37
v
3.8 Wide variation in SFDR for small changes in input amplitude. The solid vertical
line represents a level of the reconstructed quantized signal, and the dotted lines
arethequantizerthresholds. ThefigurespanstwoLSBofthequantizerinputrange. 38
3.9 The first harmonics of the LCADC output with ZCD delay variation. The input is
a20kHz1Vpeaksinewave. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.10 Impact of dispersion on SDR, 500 harmonics considered. The input is a full scale
sinusoidofthespecifiedfrequency. . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.11 Dispersion as a function of stage bandwidth for a 3-stage cascade of identical
single-time-constantstages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.12 Visualizationofthefunction p (∆,t)definedforallreal∆. . . . . . . . . . . . . . 45
0
3.13 Within one period of a full-scale sine wave there are 2N+1 level crossings, which
occurattimess relativetothebeginningofeachperiod. . . . . . . . . . . . . . . 45
i
3.14 Decomposition of a noisy TR (t) signal (a) into the ideal noiseless TR (t) signal
m m
(b)andapulsesequencerepresentingjitterduetonoise(c). . . . . . . . . . . . . 46
3.15 NoisecorruptsthepathoftheZCDoutputvoltage,causingthezerocrossingtobe
disturbedrandomly. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.16 Simulated LCADC noise with ZCD jitter, over a 100 MHz span with a 10 kHz
input. Resolutionbandwidthis100Hz. . . . . . . . . . . . . . . . . . . . . . . . 51
3.17 Detail of Fig. 3.16 over a 2 MHz span with the same RBW = 100 Hz. At low
frequencies,theimpulseapproximationisstillvalid. . . . . . . . . . . . . . . . . 52
vi
3.18 SimulatedLCADCnoisewithZCDjitter,overa100MHzspanwitha1kHzinput.
Resolutionbandwidthis10Hz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.19 Detail of Fig. 3.18 over a 2 MHz span, with RBW = 10 Hz. Note the LCADC
distortion components have moved closer in, but other than that the impulse ap-
proximationstillpredictsthenoiselevel. . . . . . . . . . . . . . . . . . . . . . . . 54
4.1 ToplevelLCADCblockdiagram. . . . . . . . . . . . . . . . . . . . . . . . . . . 58
4.2 Twomethodsforreducingthesamplingrate. . . . . . . . . . . . . . . . . . . . . . 60
4.3 Thebehaviorofanidealadaptiveresolutionscheme(a)andtheproposed(b). . . . 61
4.4 If the input slope changes, the trailing boundary can catch the input leading to
oscillations, shown in (a). The alternative trailing boundary behavior shown in (b)
doesnotsufferthisproblem. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
4.5 If the input crosses a threshold during a resolution change, there is a quantization
error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
4.6 Asynchronous timing generator formed with an 11-tap delay line, each with 4-bit
control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
4.7 The timing edges from the delay line are launched by either anUP trigger or DN
trigger. If the line has not finished propagating when then next trigger arrives, it
restartsfromthebeginning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
vii