Continuous-Time Delta-Sigma Modulators for Wireless Communication Andersson, Mattias

142 Pages·2016·7.05 MB·English

Continuous-Time Delta-Sigma Modulators for Wireless Communication
Andersson, Mattias
2014
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Citation for published version (APA):
Andersson, M. (2014). Continuous-Time Delta-Sigma Modulators for Wireless Communication. [Doctoral Thesis
(compilation), Department of Electrical and Information Technology]. Department of Electrical and Information
Technology, Lund University.
Total number of authors:
1
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LUND UNIVERSITY
PO Box 117
221 00 Lund
[phone]
Continuous-Time Delta-Sigma
Modulators for Wireless
Communication
Mattias Andersson
Doctoral Dissertation
Lund, March 2014
Department for Electrical and Information Technology
Lund University
P.O. Box 118
SE-22100 LUND
SWEDEN
ISSN 1654-790X, no.55
ISBN 978-91-7473-785-1 (print)
ISBN 978-91-7473-786-8 (pdf)
Series of licentiate and doctoral dissertations.
c Mattias Andersson 2014.
(cid:13)
Produced using LATEX Documentation System.
Printed in Sweden by Tryckeriet i E-huset, Lund.
March 2014.
To Lisa

Abstract
The ever increasing data rates in wireless communication require analog to
digital converters (ADCs) with greater requirements on speed and accuracy,
while being power efficient to prolong battery life. This dissertation contains
an introduction to the field and five papers that focus on the continuous-time
(CT) ∆Σ modulator (DSM) as ADC.
Paper I analyses the performance degradation of dynamic nonlinearity in
thefeedbackDACoftheDSM,causedbyV mismatchinthecurrent-switching
th
(differential) pair of a current-steering DAC. A model is developed to study
return-to-zero (RZ) and non-return-to-zero (NRZ) feedback DACs, with and
withoutdata-weightedaveraging(DWA),whereanRZDACwithDWArecov-
ers the performance.
PaperIIandIIIpresentsafeedbackschemeforimprovedrobustnessagainst
variationsinloopdelay. AnRZpulse,centeredintheclockperiod,isusedinthe
innermost feedback path which has the highest sensitivity to loop delay, while
NRZ pulses are adopted in the outer feedback paths to reduce the sensitivity
to clock jitter and lower the integrator slew rate requirements. Furthermore,
the otherwise obligatory loop delay compensation path (e.g. an additional
DAC and adder) could be omitted to reduce hardware complexity. A discrete-
time model of the feedback scheme confirms a negligible loss in performance.
The 3rd-order CT DSM in 65nm CMOS with 9MHz LTE bandwidth achieves
69/71dB SNDR/SNR and consumes 7.5mW from a 1.2V supply. Measure-
mentswithOFDMsignalsverifyanimprovedtolerancetoblockersoutsidethe
signal band of the DSM.
Paper IV and V present two filtering ADCs, where the DSM is merged
into the channel select filter to suppress the noise from the DSM. The first
andsecondprototypesprovidea2nd-and3rd-orderchannelselectfilteringand
improve the SNDR of the DSM by 14dB and 20dB, respectively, which in
theory can be exploited to reduce the DSM power consumption by four to
eight times.
The first prototype has a 288MHz clock frequency, a 9MHz LTE band-
width, a 2nd-order Butterworth filter response with 12dB gain, an input-
referrednoiseof8.1nV/√Hz,anin/out-of-bandIIP3of11.5/27dBV ,anda
rms
powerconsumptionof11.3mW.Thesecondprototypeisclockedat576/288MHz
with an 18.5/9MHz LTE bandwidth, a Chebyshev filter response with 26dB
gain, a low input-referred noise of 5nV/√Hz, and an in/out-of-band IIP3 of -
8.5/20dBV , with a power consumption of 7.9/5.4mW for 2xLTE20/LTE20
rms
mode. The prototype was characterized for OFDM modulated blockers and
essentially meets the cellular standard LTE Rel. 11. A delay, introduced by
thefeedbackDAC,iscompensatedbyadjustingthefiltercoefficientstorestore
the original Chebyshev filter function.
v
vi Abstract
Both prototypes have state-of-the-art power efficiency compared to other
filteringADCsandarecomparableorbetterthanastand-alonefilter. Further-
more,thefilteringADCprovidesbothfilteringandA/Dconversion,whichsug-
gests that the A/D conversion is included in a power efficient manner, broadly
speaking ”for free”.
Popul¨arvetenskaplig
sammanfattning
Tr˚adl¨os kommunikation mellan olika batteridrivna enheter s˚asom smarta tele-
foner, anv¨ands dagligen i v˚ara liv. Kommunikationen sker ofta via internet
med h¨ogkvalitativa bilder, filmer och ljud, vilket kr¨aver h¨ogre datahastigheter
identr˚adl¨osamottagaren(radiomottagaren). Denh¨ogrehastigheten¨okarpre-
standakraven p˚a komponenterna i mottagarkedjan, vilket generellt kr¨aver en
h¨ogre str¨omf¨orbrukning. S˚aledes ¨ar det viktigt att f¨orb¨attra b˚ade prestanda
och energieffektivitet i komponenterna, s˚a att de h¨ogre datahastigheterna kan
n˚as f¨or en rimlig str¨omf¨orbrukning.
Enbegr¨ansandekomponentimottagarkedjan¨aranalog-till-digitalomvand-
laren(ADC:n),somtaremotdenanalogaradiosignalenochomvandlardentill
en digital representation (ettor och nollor) som sedan avkodas i efterf¨oljande
block. Denh¨aravhandlingeninneh˚allerfemvetenskapligaartiklaromtekniker
som f¨orb¨attrar en vanligt f¨orekommande typ av ADC i radiomottagare, n¨amli-
gen delta-sigma modulatorn (DSM). En DSM ¨ar ett˚aterkopplat system som
i sig internt inneh˚aller b˚ade en ADC och flera DAC:ar (digital-till-analog om-
vandlare). VarjeDSManv¨anderistorleksordningen0.1mm2kiselytavidtillverkn-
ing i en s˚a kallad 65nm CMOS process och f¨orbrukar i storleksordningen 5-
10mW i effekt. De tv˚a viktigaste l¨osningarna som presenteras i avhandlingen
beskrivs nedan:
Den f¨orsta tekniken s¨anker ka¨nsligheten mot f¨ordr¨ojningar internt i DSM,
vilket g¨or den mer robust mot variationer i tillverkningsprocessen och f¨oren-
klar utvecklingsarbetet. Dessutom ¨ar det m¨ojligt att ta bort en av de interna
DAC:arna och p˚a s˚a s¨att spara str¨om och yta p˚a chipet. L¨osningen anv¨ander
en annan slags puls i en av DAC:arna och ¨ar verifierad med m¨atningar av ett
chip.
Den andra tekniken flyttar analog-till-digital omvandlaren in i ett filter
f¨or att skapa en filtrerande ADC. Ett filter anv¨ands ofta f¨ore ADC:n f¨or att
s¨anka prestandakraven p˚a ADC:n och totalt sett ge en l¨agre effektf¨orbrukn-
ing. F¨ordelen med den filtrerande ADC:n ¨ar att kraven p˚a ADC:n blir ¨annu
l¨agre, vilket m¨ojligg¨or en s¨ankning av effektf¨orbrukningen i ADC:n med mer
¨anfyrag˚anger. Konceptet¨arverifieratmedtv˚atillverkadechip, d¨ardetandra
chipet st¨odjer en av de senaste standarderna f¨or mobilkommunikation, ”long-
term evolution” (LTE) release 11. Den filtrerande ADC:n har lika bra eller
b¨attre energieffektivitet j¨amf¨ort med andra publicerade filter, vilket indikerar
att sj¨alva analog-till-digital omvandligen sker effektivt.
Doktorandtj¨anstenochkiseltillverkningenharfinansieratsavprojektenDe-
sign Methods for Radio Architectures GOing Nanoscale (DRAGON), System-
design-On-Silicon (SOS) och ST Microeletronics.
vii

Contents
Abstract v
Popul¨arvetenskaplig sammanfattning vii
Contents ix
Preface xi
Acknowledgments xiii
List of Acronyms xv
List of Symbols xix
Introduction 1
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Research contributions . . . . . . . . . . . . . . . . . . . . 2
1.3 Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 The radio receiver . . . . . . . . . . . . . . . . . . . . . . 5
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2 Characterization of receiver blocks . . . . . . . . . . . . . 7
2.2.1 Input referred representation . . . . . . . . . . . . . 7
2.2.2 Noise . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2.3 Compression point, P and CP . . . . . . . . . . 8
1dB
2.2.4 Intermodulation intercept point . . . . . . . . . . . 8
3 Continuous-time ∆Σ modulators . . . . . . . . . . . . . . 11
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.2 Basics of filtering ADCs . . . . . . . . . . . . . . . . . . . 12
3.2.1 The term filtering ADC . . . . . . . . . . . . . . . . 14
3.2.2 Previous work . . . . . . . . . . . . . . . . . . . . . 14
NTF and STF trade-offs . . . . . . . . . . . . . . 15
Feed-forward modulators . . . . . . . . . . . . . 15
Improved selectivity and noise shaping . . . . . . 16
3.3 Performance comparison of filtering ADCs . . . . . . . . . 16
3.3.1 Comparison with filters . . . . . . . . . . . . . . . . 17
3.4 Feedback DAC pulse . . . . . . . . . . . . . . . . . . . . . 19
3.4.1 Fixed loop delay . . . . . . . . . . . . . . . . . . . . 20
3.4.2 Variations in loop delay . . . . . . . . . . . . . . . . 21
3.4.3 z-domain analysis of loop delay variations . . . . . . 22
ix