Construction of a low-ripple inverter with accurate phase control for cali

128 Pages·2014·5.7 MB·English

G PWM Full-bridge
PLL
controller converter
C
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o Reference u
r
lta instrument re
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e t
Device
Under Test
Construction of a low-ripple inverter
with accurate phase control for cali-
bration of measurement equipment
MasterofScienceThesisinElectricPowerEngineering
ADAM EINARSSON
ALI ASGARI VAND
DepartmentofEnergyandEnvironment
DivisionofElectricPowerEngineering
CHALMERS UNIVERSITY OF TECHNOLOGY
Go¨teborg,Sweden2014

Construction of a low-ripple inverter
with accurate phase control for
calibration of measurement equipment
ADAMEINARSSON
ALIASGARIVAND
DepartmentofEnergyandEnvironment
DivisionofElectricPowerEngineering
CHALMERSUNIVERSITYOFTECHNOLOGY
Go¨teborg,Sweden2014
Constructionofalow-rippleinverterwithaccuratephasecontrolforcalibrationof
measurementequipment
ADAMEINARSSON
ALIASGARIVAND
©ADAMEINARSSON
ALIASGARIVAND,2014.
DepartmentofEnergyandEnvironment
DivisionofElectricPowerEngineering
ChalmersUniversityofTechnology
SE–41296Go¨teborg
Sweden
Telephone[phone]
Cover:
Overviewofacalibrationsystemwithaphase-lockedloop(PLL)foraccuratephase
controlbetweencurrentandvoltagebranch.
ChalmersBibliotek,Reproservice
Go¨teborg,Sweden2014
Constructionofalow-rippleinverterwithaccuratephasecontrolforcalibrationof
measurementequipment
ADAMEINARSSON
ALIASGARIVAND
DepartmentofEnergyandEnvironment
DivisionofElectricPowerEngineering
ChalmersUniversityofTechnology
Abstract
Forthedesignofanelectricpowersystem,knowledgeoftheparametersofallthecompo-
nentsisessential.Especiallythetransformersareanimportantpartofthis.Itistherefore
important that the measurement equipment for determining these values is accurate. In
no-load operation, the transformer mainly consumes reactive power. A small error in
the measurement of the power angle therefore gives a large error in the active power
calculation. The Technical Research Institute of Sweden, SP, performs calibrations of
thesemeasurementsystems.Calibrationsaredonebymeasuringareferencevoltage and
generatingacurrentinasecondarycircuitwithacontrollablephaseshift.Thevoltageand
current makeup avirtual powerand are measuredby the reference instrument andby the
equipmenttobecalibrated.
Thisthesisdescribestheworkofconstructingasingle-phasefull-bridgeconverterfor
inverteroperationwithaccuratephasecontrolofthecurrentinthesecondarycircuitrelative
tothesinusoidalreferencevoltage.ACompactRIO™systemfromNationalInstruments
is used to control the converter through pulse-width modulation (PWM). An analogue-
to-digital converter (ADC) module is used to sample the reference signal and a digital
I/O module outputs the PWM signals. A phase-locked loop (PLL) algorithm estimates
the phase of the sampled reference voltage to use in the generation of the PWM signals.
ThreedifferentPLLshavebeenimplementedwithLabVIEW™codeontheFPGAchip
of the CompactRIO™system. The three PLLs are the inverse Park PLL (IP-PLL) based
on the synchronous reference frame, the enhanced PLL (E-PLL) based on the gradient
descent method and the KF-PLL based on the Kalman filter. Both the E-PLL and the
KF-PLL are also based on models for estimating specific signal components. With the
basicconfigurations,theIP-PLLshowssuperiorperformanceinsimulationswithdcoffset
and low-orderharmonic inthe input signal. Thisis due toits low-pass filters. Whilethe
standard deviation in the phase error of the IP-PLL was 50 µrad it was 350 µrad for
the E-PLL and 570 µrad for the KF-PLL with a dc offset at 1.8 % of the fundamental
amplitudeintheinputsignal.Withathirdharmonicat10%ofthefundamentalamplitude,
thestandard deviations ofthephase errors were50.3µrad,776 µradand 889µradfor the
IP-PLL,theE-PLLandtheKF-PLLrespectively.ByextendingtheE-PLLandtheKF-PLL
toincludeestimationofdc-offsetandharmonics,thesesteady-stateerrorsarecompletely
eliminated.However,especially theKF-PLLbut alsotheE-PLL,is muchmorecomplex
andhardertotunethantheIP-PLL.WhenimplementedonCompactRIO™ theKF-PLL
includingestimationofdcoffsetgotthebestresultswithastandarddeviationinthephase
errorof5.1µradcomparedto49.2µradfortheIP-PLLwithminimizedcut-offfrequency
iii
ofthelow-passfiltersforadcoffsetof0.41%ofthefundamentalamplitudeintheinput
signal.
It is shown that the phase error of the complete system can be kept below a standard
deviation of 600 µrad, with a stable reference voltage. The pattern of the phase error
however has an oscillatory shape with a frequency of about 0.12 Hz. This is thought to
originatefromadriftintheclockoftheADCmodulerelativetotheclockoftheFPGAin
theCompactRIO™system.Thismustbefurtherinvestigated.Additionally,theamplitude
accuracy of the fundamental frequency is found to have a standard deviation of about
63ppm,withadc-sourcespecifiedtobeaccurateto50ppm.
Indexterms:PWM,full-bridgeconverter,IGBT,CompactRIO™,Kalmanfilter,PLL.
iv
Acknowledgements
ThisworkhasbeencarriedoutattheDepartmentofEnergyandEnvironmentatChalmers
UniversityofTechnologyinGo¨teborgandTheTechnicalResearchInstituteofSweden,
SP,inBora˚sfromJanuarytoJuneof2014.WewouldliketothankAndersLindskog,Alf-
PeterElg,StefanSvenssonandAllanBergmanatSPforhelpingoutwithmeasurements,
supplyofequipment,helpwithLabVIEW™codeanddiscussionabouttheproblem.Many
thanksaredirectedtowardsRobertKarlssonatChalmersforindispensablehelpwiththe
practicalissues ofconstructinga converter.Weare alsothankfultowards ourexaminerat
Chalmers,StefanLundberg,forgivinggoodfeedbackontheworkandthereportandfor
gooddiscussionsaboutproblems.
AdamEinarsson,AliAsgariVand
Go¨teborg,Sweden,2014
v
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Contents
Abstract iii
Acknowledgements v
Contents vii
ListofAbbreviations ix
1 Introduction 1
1.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Previouswork . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.3 Purpose/Aim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Technicalbackground 5
2.1 Phasetracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1.1 ThegeneralPLLalgorithm . . . . . . . . . . . . . . . . . . . . . 5
2.1.2 ThesynchronousreferenceframePLL . . . . . . . . . . . . . . . 6
2.1.3 TheenhancedPLL . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1.4 TheKalmanfilter . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2 Single-phasefull-bridgeconverter . . . . . . . . . . . . . . . . . . . . . 16
2.2.1 Pulse-widthmodulation . . . . . . . . . . . . . . . . . . . . . . 16
2.3 Theinsulated-gatebipolartransistor . . . . . . . . . . . . . . . . . . . . 20
2.3.1 Conductionlosses . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.3.2 Switchinglosses . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.3.3 Thermalconsiderations . . . . . . . . . . . . . . . . . . . . . . . 24
2.3.4 Gatedriver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.4 CompactRIO™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.4.1 Thefieldprogrammablegatearray . . . . . . . . . . . . . . . . . 26
2.4.2 LabVIEW™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3 Simulations 29
3.1 Phasetracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.1.1 ThesynchronousreferenceframePLL . . . . . . . . . . . . . . . 29
3.1.2 TheenhancedPLL . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.1.3 TheKalmanfilterPLL . . . . . . . . . . . . . . . . . . . . . . . 34
3.1.4 Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.2 Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
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Contents
3.2.1 Loadmeasurements . . . . . . . . . . . . . . . . . . . . . . . . 47
3.2.2 Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4 Design 59
4.1 Realtimecontrolsystemimplementation . . . . . . . . . . . . . . . . . 59
4.1.1 Userinterface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
4.1.2 FPGAimplementation . . . . . . . . . . . . . . . . . . . . . . . 61
4.2 Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
4.2.1 Selectionofdc-linkcapacitors . . . . . . . . . . . . . . . . . . . 66
4.2.2 SelectionofIGBTmodule . . . . . . . . . . . . . . . . . . . . . 67
4.2.3 Selectionofgatedriver . . . . . . . . . . . . . . . . . . . . . . . 69
4.2.4 Selectionofheatsink . . . . . . . . . . . . . . . . . . . . . . . . 71
4.2.5 CompactRIO™-to-gatedriverinterface . . . . . . . . . . . . . . 72
4.2.6 Assemblyandgatedriversettings . . . . . . . . . . . . . . . . . 72
5 Testsandmeasurements 75
5.1 PhasetrackingoftheimplementedPLLsonCompactRIO™ . . . . . . . 75
5.1.1 TheinverseParkPLL . . . . . . . . . . . . . . . . . . . . . . . . 75
5.1.2 TheenhancedPLL . . . . . . . . . . . . . . . . . . . . . . . . . 77
5.1.3 TheKalmanfilterPLL . . . . . . . . . . . . . . . . . . . . . . . 77
5.2 Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
5.2.1 Gatedriver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
5.2.2 Switchinginducedvoltagespikes . . . . . . . . . . . . . . . . . 83
5.2.3 Losses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
5.2.4 Harmonicsattenuation . . . . . . . . . . . . . . . . . . . . . . . 87
5.3 Phaseandamplitudejitter . . . . . . . . . . . . . . . . . . . . . . . . . . 87
6 Conclusionsandfuturework 93
6.1 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
6.2 Futurework . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
References 97
A MATLAB® code 103
A.1 TheKalmanfilter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
B Kalmanfiltergainfactorcoefficients 105
C LabVIEW™code 107
C.1 RTcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
C.2 Hostcomputer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
C.3 FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
C.3.1 PWMcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . 111
C.3.2 TheinverseParkPLL . . . . . . . . . . . . . . . . . . . . . . . . 112
C.3.3 TheenhancedPLL . . . . . . . . . . . . . . . . . . . . . . . . . 113
C.3.4 TheKalmanfilterPLL . . . . . . . . . . . . . . . . . . . . . . . 113
viii