Computer Arithmetic

207 Pages·2006·2.11 MB·English

Computer Arithmetic
Hossam A. H. Fahmy, Shlomo Waser, and Michael J. Flynn
Draft revised version, based on the book:
Introduction to Arithmetic for Digital Systems Designers
by Shlomo Waser and Michael J. Flynn
Originally published by Holt, Rinehard & Winston,
New York, 1982 (Out of print)
2
Contents
1 Numeric Data Representation 11
1.1 Infinite aspirations and finite resources . . . . . . . . . . . . . . . . . . . . . . . . 12
1.2 Natural Numbers, Finitude, and Modular Arithmetic . . . . . . . . . . . . . . . . 13
1.2.1 Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.2.2 Extending Peano’s Numbers. . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.3 Integer Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.3.1 Complement Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.3.2 Radix Complement Code—Subtraction Using Addition . . . . . . . . . . 18
1.3.3 Diminished Radix Complement Code. . . . . . . . . . . . . . . . . . . . . 20
1.4 Implementation of Integer Operations . . . . . . . . . . . . . . . . . . . . . . . . 23
1.4.1 Negation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.4.2 Two’s Complement Addition . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.4.3 One’s Complement Addition . . . . . . . . . . . . . . . . . . . . . . . . . 25
1.4.4 Computing Through the Overflows . . . . . . . . . . . . . . . . . . . . . . 26
1.4.5 Arithmetic Shifts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
1.4.6 Multiplication. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
1.4.7 Division . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
1.5 Going far and beyond . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
1.6 Further readings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
1.7 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
1.8 Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2 Floating over the vast seas 37
2.1 Motivation and Terminology; or the why? and what? of floating point. . . . . . . 37
3
4 CONTENTS
2.2 Properties of Floating Point Representation . . . . . . . . . . . . . . . . . . . . . 39
2.2.1 Lack of Unique Representation . . . . . . . . . . . . . . . . . . . . . . . . 39
2.2.2 Range and Precision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2.2.3 Mapping Errors: Overflows, Underflows, and Gap. . . . . . . . . . . . . . 42
2.3 Reviewing floating point standards . . . . . . . . . . . . . . . . . . . . . . . . . . 43
2.3.1 Prior formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
2.4 Floating Point Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
2.4.1 Addition and Subtraction . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
2.4.2 Multiplication. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
2.4.3 Division . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
2.5 Problems in Floating Point Computations . . . . . . . . . . . . . . . . . . . . . . 50
2.5.1 Representational error analysis and radix tradeoffs . . . . . . . . . . . . . 50
2.5.2 Loss of Significance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
2.5.3 Rounding: Mapping the Reals into the Floating Point Numbers . . . . . . 56
2.6 Comparing the different systems . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
2.7 Reading the fine print in the standard . . . . . . . . . . . . . . . . . . . . . . . . 58
2.7.1 Rounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
2.7.2 Exceptions and What to Do in Each Case . . . . . . . . . . . . . . . . . . 62
2.7.3 Analysis of the IEEE 754 standard . . . . . . . . . . . . . . . . . . . . . . 67
2.8 Exact and interval arithmetic (Incomplete section) . . . . . . . . . . . . . . . . . 70
2.9 Decimal arithmetic (Incomplete section) . . . . . . . . . . . . . . . . . . . . . . . 71
2.10 Cray Floating Point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
2.10.1 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
2.10.2 Machine Maximum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
2.10.3 Machine Minimum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
2.10.4 Treatment of Zero . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
2.10.5 Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
2.10.6 Overflow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
2.11 Additional Readings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
2.12 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
2.13 Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
CONTENTS 5
3 Are there any limits? 79
3.1 The logic level and the technology level . . . . . . . . . . . . . . . . . . . . . . . 80
3.2 The Residue Number System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
3.2.1 Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
3.2.2 Operations in the Residue Number System . . . . . . . . . . . . . . . . . 83
3.2.3 Selection of the Moduli . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
3.2.4 Operations with General Moduli . . . . . . . . . . . . . . . . . . . . . . . 86
3.2.5 Conversion To and From Residue Representation . . . . . . . . . . . . . . 87
3.2.6 Uses of the Residue Number System . . . . . . . . . . . . . . . . . . . . . 91
3.3 The limits of fast arithmetic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
3.3.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
3.3.2 Levels of evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
3.3.3 The (r,d) Circuit Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
3.3.4 First Approximation to the Lower Bound . . . . . . . . . . . . . . . . . . 95
3.3.5 Spira/Winograd bound applied to residue arithmetic . . . . . . . . . . . . 97
3.3.6 Winograd’s Lower Bound on Multiplication . . . . . . . . . . . . . . . . . 98
3.4 Modeling the speed of memories . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
3.5 Modeling the multiplexers and shifters . . . . . . . . . . . . . . . . . . . . . . . . 102
3.6 Additional Readings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
3.7 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
3.8 Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
4 Addition and Subtraction (Incomplete chapter) 109
4.1 Fixed Point Algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
4.1.1 Historical Review . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
4.1.2 Conditional Sum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
4.1.3 Carry-Look-Ahead Addition . . . . . . . . . . . . . . . . . . . . . . . . . . 114
4.1.4 Canonic Addition: Very Fast Addition and Incrementation . . . . . . . . 118
4.1.5 Ling Adders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
4.1.6 Simultaneous Addition of Multiple Operands: Carry-Save Adders. . . . . 129
4.2 Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
6 CONTENTS
5 Go forth and multiply 133
5.1 Simple multiplication methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
5.2 Simultaneous Matrix Generation and Reduction. . . . . . . . . . . . . . . . . . . 138
5.2.1 Partial Products Generation: Booth’s Algorithm . . . . . . . . . . . . . . 140
5.2.2 Using ROMs to Generate Partial Products . . . . . . . . . . . . . . . . . 143
5.2.3 Partial Products Reduction . . . . . . . . . . . . . . . . . . . . . . . . . . 146
5.3 Iteration and Partial Products Reduction . . . . . . . . . . . . . . . . . . . . . . 149
5.3.1 A Tale of Three Trees . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
5.4 Iterative Array of Cells. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
5.5 Detailed Design of Large Multipliers . . . . . . . . . . . . . . . . . . . . . . . . . 160
5.5.1 Design Details of a 64×64 Multiplier . . . . . . . . . . . . . . . . . . . . 160
5.5.2 Design Details of a 56×56 Single Length Multiplier . . . . . . . . . . . . 165
5.6 Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
6 Division (Incomplete chapter) 171
6.1 Subtractive Algorithms: General Discussion . . . . . . . . . . . . . . . . . . . . . 171
6.1.1 Restoring and Nonrestoring Binary Division . . . . . . . . . . . . . . . . . 171
6.1.2 Pencil and Paper Division . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
6.2 Multiplicative Algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
6.2.1 Division by Series Expansion . . . . . . . . . . . . . . . . . . . . . . . . . 175
6.2.2 The Newton–Raphson Division . . . . . . . . . . . . . . . . . . . . . . . . 177
6.3 Additional Readings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
6.4 Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
7 Solutions 183
Solutions to Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
List of Figures
2.1 IEEE single and double floating point number format. . . . . . . . . . . . . . . . 44
3.1 The (r,d) circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
3.2 Time delays in a circuit with 10 inputs and (r,d)=(4,2). . . . . . . . . . . . . . 96
3.3 The (r,d) network. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
3.4 A simple memory model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
4.1 Example of the conditional sum mechanism. . . . . . . . . . . . . . . . . . . . . . 111
4.2 4-bit conditional sum adder slice with carry-look-ahead (gate count=45). . . . . 113
4.3 16-bit conditional sum adder. The dotted line encloses a 4-bit slice with internal
lookahead. Therectangularbox(onthebottom)acceptsconditionalcarriesand
generates fast true carries between slices. The worst case path delay is seven gates.114
4.4 4-bit adder slice with internal carry-look-ahead (gate count = 30). . . . . . . . . 116
4.5 Four group carry-look-ahead generator (gate count = 14). . . . . . . . . . . . . . 117
4.6 64-bit addition using full carry-look-ahead. . . . . . . . . . . . . . . . . . . . . . 118
4.7 Addition of three n-bit numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
4.8 Addition of four n-bit numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
5.1 A simple implementation of the add and shift multiplication. . . . . . . . . . . . 136
5.2 A variation of the add and shift multiplication. . . . . . . . . . . . . . . . . . . . 136
5.3 Multiplying two 8-bit operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
5.4 Generationoffivepartialproductsin8×8multiplication,usingmodifiedBooth’s
algorithm (only four partial products are generated if the representation is re-
stricted to two’s complement). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
5.5 Implementationof8×8multiplicationusingfour256×8ROMs,whereeachROM
performs 4×4 multiplication. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
7
8 LIST OF FIGURES
5.6 Using ROMs for various multiplier arrays . . . . . . . . . . . . . . . . . . . . . . 145
5.7 Wallace tree. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
5.8 Wallace tree reduction of 8×8 multiplication, using carry save adders (CSA). . . 148
5.9 The (5,5,4) reduces the five input operands to one operand. . . . . . . . . . . . . 149
5.10 Some generalized counters from Stenzel Stenzel et al. [1977]. . . . . . . . . . . . . 150
5.11 12×12 bit partial reduction using (5,5,4) counters . . . . . . . . . . . . . . . . . 151
5.12 Earle latch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
5.13 Slice of a simple iteration tree showing one product bit. . . . . . . . . . . . . . . 153
5.14 Slice of tree iteration showing one product bit. . . . . . . . . . . . . . . . . . . . 154
5.15 Slice of low level tree iteration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
5.16 Iteration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
5.17 5×5 unsigned multiplication. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
5.18 1–bit adder cell.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
5.19 5×5 two’s complement multiplication [PEZ 70]. . . . . . . . . . . . . . . . . . . 159
5.20 2–bit adder cell.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
5.21 Block diagram of 2×4 iterative multiplier. . . . . . . . . . . . . . . . . . . . . . 161
5.22 12×12 two’s complement multiplication A = X·Y+K. Adapted from [Ghest,
1971]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
5.23 A 64×64 multiplier using 8×8 multipliers. . . . . . . . . . . . . . . . . . . . . . 163
5.24 Partial products generation of 64×64 multiplication . . . . . . . . . . . . . . . . 163
5.25 Using (5,5,4)s to reduce various column heights . . . . . . . . . . . . . . . . . . . 164
5.26 Reduction of the partial products of height 15 . . . . . . . . . . . . . . . . . . . . 166
5.27 Partial products generation in a 56×56 multiplication. . . . . . . . . . . . . . . 167
6.1 Partial remainder computations in restoring and nonrestoring division . . . . . . 174
6.2 Plot of the curve f(X)=0.75− 1 and its tangent at f(X ), where X =1 (first
X 1 1
guess). f0(x )= δy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
1 δx
List of Tables
1.1 A 4 bits negabinary system. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.1 Maximum and minimum exponents in the single and double IEEE formats. . . . 44
2.2 Encodings of the special values and their meanings.. . . . . . . . . . . . . . . . . 44
2.3 Comparison of floating point specification for three popular computers.. . . . . . 46
2.4 IEEE and DEC decoding of the reserved operands . . . . . . . . . . . . . . . . . 47
2.5 Tarde-off between radix and representational errors . . . . . . . . . . . . . . . . . 53
2.6 Underflow/overflow designations in Cray machines. . . . . . . . . . . . . . . . . . 74
3.1 A Partial List of Moduli and Their Prime Factors. . . . . . . . . . . . . . . . . . 86
3.2 Time delay of various components in terms of number of FO4 delays. r is the
maximum fan-in of a gate and n is the number of inputs. . . . . . . . . . . . . . 104
4.1 Addition speed of hardware realizations and lower bounds . . . . . . . . . . . . . 128
5.1 Encoding 2 multiplier bits by inspecting 3 bits, in the modified Booth’s algorithm.141
5.2 Extension of the modified Booth’s algorithm. . . . . . . . . . . . . . . . . . . . . 142
5.3 Summaryofmaximumheightofthepartialproductsmatrixforthevariouspartial
generation schemes where n is the multiple size. . . . . . . . . . . . . . . . . . . . 144
9
10 LIST OF TABLES