Computer-Aided Design of Microfluidic Very Large Scale Integration (mVLSI) Biochips: Design Automation, Testing, and Design-for-Testability

151 Pages·2017·6.88 MB·English

by  Kai Hu

Kai Hu · Krishnendu Chakrabarty
Tsung-Yi Ho
Computer-Aided
Design of Microfluidic
Very Large Scale
Integration (mVLSI)
Biochips
Design Automation, Testing, and
Design-for-Testability
fl
Computer-Aided Design of Micro uidic Very Large
Scale Integration (mVLSI) Biochips
Kai Hu Krishnendu Chakrabarty
(cid:129)
Tsung-Yi Ho
Computer-Aided Design
fl
of Micro uidic Very Large
Scale Integration (mVLSI)
Biochips
Design Automation, Testing,
and Design-for-Testability
123
KaiHu Tsung-Yi Ho
Oracle, Inc. Department ofComputer Science
SantaClara, CA National TsingHua University
USA Hsinchu
Taiwan
Krishnendu Chakrabarty
Department ofECE
Duke University
Durham, NC
USA
ISBN978-3-319-56254-4 ISBN978-3-319-56255-1 (eBook)
DOI 10.1007/978-3-319-56255-1
LibraryofCongressControlNumber:2017935833
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To my beloved parents,
Qingyuan Hu and Guoling Huang.
To those days and nights at graduate school.
Forever Duke!
—Kai Hu
Preface
Flow-based microfluidic biochips constitute an emerging technology for the
automation of biochemical procedures. Recent advances in fabrication techniques
have enabled the development of these devices. Increasing integration levels pro-
videbiochipswithtremendouspotential;alargenumberofbioassays,i.e.,protocols
for biochemistry, can be processed independently, simultaneously, and automati-
cally on a coin-sized microfluidic platform. However, the increase in integration
level introduces new challenges in the design optimization and testing of these
devices, which impede their further adoption and deployment.
This book is focused on enhancing the automated design and the use of
flow-based microfluidic biochips and on developing a set of solutions to facilitate
thefullexploitationofdesigncomplexitiesthatarepossiblewithcurrentfabrication
techniques. Four key research challenges are addressed in the book; these include
design automation, wash optimization, testing, and defect diagnosis.
Despite the increase in the number of on-chip valves, designers are still using
full-custommethodologiesinvolvingmanymanualstepstoimplementthesechips.
Since these chips can easily have thousands of valves, a manual design procedure
canbetime-consuminganderror-prone,anditcanresultininefficientdesigns.This
book presents the first problem formulation for automated control-layer design in
flow-based microfluidic biochips and describes a systematic approach for solving
this problem. Our goal is to find an efficient routing solution for control-layer
design with a minimum number of control pins.
Theproblemofcontaminationremovalinflow-basedmicrofluidicbiochipsmust
also be addressed. Applications in biochemistry require high precision to avoid
erroneous assay outcomes, and they are vulnerable to contamination between two
fluidicflowswithdifferentbiochemistries.Thisbookproposesthefirstapproachfor
automatedwashoptimizationforcontaminationremovalinflow-basedmicrofluidic
biochips. The proposed approach ensures effective cleaning and targets the gen-
eration of wash pathways to clean all contaminated microchannels with minimum
execution time under physical constraints.
Another practical problem addressed in this book is the lack of test techniques
forscreeningdefectivebiochipsbeforetheyareusedforbiochemicalanalysis.This
vii
viii Preface
bookpresentsanefficientapproachforautomatedtestingofflow-basedmicrofluidic
biochips.Thetesttechniqueisbasedonabehavioralabstractionofphysicaldefects
in microchannels and valves. The flow paths and flow control in the microfluidic
devicearemodeledasalogiccircuitcomposedofBooleangates,whichallowstest
generation to be carried out using standard automatic test-pattern generation tools.
Based on the analysis of untestable faults in the logic circuit model, we present a
design-for-testability technique that can achieve 100% fault coverage.
Finally, this book presents a technique for the automated diagnosis of leakage
andblockagedefects.Theproposedmethodtargetstheidentificationofdefecttypes
andtheirlocationsbasedontestoutcomes.Itreducesthenumberofpossibledefect
sites significantly while identifying their exact locations.
In summary, this book provides a set of optimization and testing methods for
flow-based microfluidic biochips. These methods are expected to not only shorten
the product development cycle, but also accelerate the adoption and further
development of this emerging technology by facilitating the full exploitation of
design complexities that are possible with current fabrication techniques.
Santa Clara, CA, USA Kai Hu
Durham, NC, USA Krishnendu Chakrabarty
Hsinchu, Taiwan Tsung-Yi Ho
Acknowledgements
The authors acknowledge Prof. Bhargab B. Bhattacharya from Indian Statistical
Institute,Kolkata,India,forvaluablediscussionsandcollaboration.Theauthorsalso
acknowledge Prof. Richard B. Fair from Duke University, Durham, NC and
Dr.FuqiaoYufromStanfordUniversity,Stanford,CA,forconstructivesuggestions.
KaiHuandKrishnenduChakrabartyacknowledgethefinancialsupportreceived
from the US National Science Foundation.
Tsung-Yi Ho acknowledges the financial support received from the Taiwan
Ministry of Science and Technology.
ix
Contents
1 Introduction.... .... .... ..... .... .... .... .... .... ..... .... 1
1.1 Introduction of Microfluidic Biochip Platforms .. .... ..... .... 2
1.2 Overview of Flow-Based Microfluidic Biochips.. .... ..... .... 6
1.2.1 Structure and Fabrication . .... .... .... .... ..... .... 7
1.2.2 Components .. ..... .... .... .... .... .... ..... .... 8
1.2.3 Applications .. ..... .... .... .... .... .... ..... .... 12
1.3 Challenges and Motivation.. .... .... .... .... .... ..... .... 15
1.3.1 Design Automation.. .... .... .... .... .... ..... .... 16
1.3.2 Contamination Removal .. .... .... .... .... ..... .... 16
1.3.3 Defects and Erroneous Operations .. .... .... ..... .... 17
1.4 Outline of the Book .. ..... .... .... .... .... .... ..... .... 19
References.. .... .... .... ..... .... .... .... .... .... ..... .... 20
2 Control-Layer Optimization.... .... .... .... .... .... ..... .... 25
2.1 Motivation and Related Prior Work ... .... .... .... ..... .... 26
2.2 Problem Description, Design Requirements, and Challenges . .... 26
2.2.1 Pressure-Propagation Delay.... .... .... .... ..... .... 26
2.2.2 Requirements in Control-Layer Design... .... ..... .... 27
2.2.3 Valve Addressing ... .... .... .... .... .... ..... .... 30
2.2.4 Routing of Control Channels... .... .... .... ..... .... 33
2.2.5 Placement of Control Pins. .... .... .... .... ..... .... 34
2.2.6 Relationship Between Control-Layer Optimization
and Clock-Tree Design in VLSI Circuits . .... ..... .... 34
2.3 Problem Formulation . ..... .... .... .... .... .... ..... .... 35
2.4 Algorithm Design.... ..... .... .... .... .... .... ..... .... 36
2.4.1 Routing Algorithm 1. .... .... .... .... .... ..... .... 37
2.4.2 Routing Algorithm 2. .... .... .... .... .... ..... .... 41
2.5 Experimental Results . ..... .... .... .... .... .... ..... .... 45
2.5.1 Experiments with Two Fabricated Biochips ... ..... .... 46
2.5.2 Experiments with Synthetic Benchmarks.. .... ..... .... 50
xi
xii Contents
2.6 Conclusions .... .... ..... .... .... .... .... .... ..... .... 50
References.. .... .... .... ..... .... .... .... .... .... ..... .... 51
3 Wash Optimization for Cross-Contamination Removal .. ..... .... 53
3.1 Motivation and Challenges.. .... .... .... .... .... ..... .... 54
3.2 Problem Description and Formulation . .... .... .... ..... .... 55
3.2.1 Physical Implementability of a Wash Path .... ..... .... 55
3.2.2 Execution Time for a Wash Path ... .... .... ..... .... 57
3.3 Search for a Set of Washing Paths.... .... .... .... ..... .... 62
3.3.1 Generation of the Path Dictionary... .... .... ..... .... 62
3.3.2 Storage of the Path Dictionary . .... .... .... ..... .... 64
3.3.3 Identification of Washing-Path Set .. .... .... ..... .... 65
3.3.4 Washing of Multiple Contaminant Species.... ..... .... 69
3.3.5 Complexity Analysis. .... .... .... .... .... ..... .... 71
3.4 Results: Application to Fabricated Biochips. .... .... ..... .... 72
3.4.1 Results for ChIP.... .... .... .... .... .... ..... .... 73
3.4.2 A Programmable Microfluidic Device
with an 8-by-8 Grid . .... .... .... .... .... ..... .... 77
3.5 Conclusions .... .... ..... .... .... .... .... .... ..... .... 78
References.. .... .... .... ..... .... .... .... .... .... ..... .... 79
4 Fault Modeling, Testing, and Design for Testability. .... ..... .... 81
4.1 Motivation and Challenges.. .... .... .... .... .... ..... .... 82
4.2 Defects and Fault Modeling. .... .... .... .... .... ..... .... 83
4.3 Testing Strategy . .... ..... .... .... .... .... .... ..... .... 86
4.4 Applications to Fabricated Biochip.... .... .... .... ..... .... 90
4.4.1 Logic Circuit Model . .... .... .... .... .... ..... .... 90
4.4.2 Test-Pattern Generation and Results . .... .... ..... .... 91
4.5 Automated Generation of Logic-Circuit Model... .... ..... .... 92
4.5.1 Physical Representation of Boolean Gates in Netlists. .... 92
4.5.2 Hierarchical Modeling.... .... .... .... .... ..... .... 94
4.5.3 Fault Analysis Based on ATPG Results .. .... ..... .... 97
4.6 Other Practical Concerns ... .... .... .... .... .... ..... .... 97
4.6.1 Test Cost. .... ..... .... .... .... .... .... ..... .... 98
4.6.2 Dynamic Faults..... .... .... .... .... .... ..... .... 98
4.6.3 Multiple Faults ..... .... .... .... .... .... ..... .... 99
4.7 Experimental Demonstration. .... .... .... .... .... ..... .... 99
4.7.1 Experimental Feasibility Demonstration .. .... ..... .... 99
4.7.2 Pattern Set-up Time, Measurement Time
and Refresh Time ... .... .... .... .... .... ..... .... 101
4.7.3 Experimental Demonstration I: Cell Culture Chip.... .... 103
4.7.4 Experimental Demonstration II: WGA Chip... ..... .... 106