Compensation Method of the Excess Loop Delay in Countinuous-Time Delta-Sigma ADCs Based ...

82 Pages·2014·0.67 MB·English

AN ABSTRACT OF THE THESIS OF

Jia Guo for the degree of Master of Science in Electrical and Computer Engineering
presented on February 4, 2014.

Title: Compensation Method of the Excess Loop Delay in Continuous-Time Delta-
Sigma ADCs Based on Model Matching Approach

Abstract approved:

Mario E. Magaña

Continues-Time (CT) Delta-Sigma (ΔΣ) Analog-to-Digital Converters (ADCs) have
one important constrain, namely the excess loop delay. Most previous excess lop delay
compensation methods need to know the exact value of the excess loop delay in
advance. However, the value of the excess loop delay is a uniformly distribution
random variable. In order to improve system performance with the same loop filter, a
new compensation algorithm for the excess loop delay of CT ΔΣ ADCs based on the
model matching method is presented in this thesis. By the new equivalence found by
Cherry and Snelgrove, model matching algorithm can compensate for the adverse
effects of the excess loop delay over a range of values efficiently. Compared to previous
compensation methods, the model matching algorithm is more practical because the
value of the excess loop delay varies randomly every clock period. It is proved through
simulation that our mean value based algorithm can improve the SQNR performance
of CT ΔΣ ADCs for the most probable values of the excess loop delay.
©Copyright by Jia Guo
February 4, 2014
All Rights Reserved
Compensation Method of the Excess Loop Delay in Continuous-Time Delta-Sigma
ADCs Based on Model Matching Approach

by
Jia Guo

A THESIS

submitted to

Oregon State University

in partial fulfillment of
the requirements for the
degree of

Master of Science

Presented February 4, 2014
Commencement June 2014
Master of Science thesis of Jia Guo presented on February 4, 2014

APPROVED:

Major Professor, representing Electrical and Computer Engineering

Director of the School of Electrical Engineering and Computer Science

Dean of the Graduate School

I understand that my thesis will become part of the permanent collection of Oregon
State University libraries. My signature below authorizes release of my thesis to any
reader upon request.

Jia Guo, Author
ACKNOWLEDGEMENTS

I would first like to express my sincere gratitude to my major professor, Dr. Mario E.
Magaña, for his endless efforts, excellent academic guidance and support during my
graduate life in Oregon State University. His outstanding advising not only helped me
throughout the master degree, but also thought me how to continue on my personal as
well as technical life and keep growing in the right path. I feel very honored and
privileged to have worked under his supervision.
I would also like to thank my family, especially my parents, Hongwei Guo and Yulan
Zhao. They provide me the opportunity to sit in the campus of Oregon State University.
Without their love and support from China, I can never have the chance to pursue a
graduate degree in United States.
Last but not the least, I would like to thank all my friends during my stay in Corvallis,
also the colleagues in KEC 3048. I can never forget their contribution to this thesis
during the designing and writing. Furthermore, I would like to thank my roommates,
Ming Chen and Guangxin Wang, for their friendships, helps and happiness during my
graduate degree pursuing days.
LIST OF CONTENTS

Page
1.  Introduction ................................................................................................................. 1 
1.1  Motivation .............................................................................................................1 
1.2  Thesis Organization ..............................................................................................3 
2.  Technical Background ................................................................................................ 4 
2.1  The Necessity of Oversampling Converters .........................................................4 
2.2  Delta-Sigma (ΔΣ) ADCs ....................................................................................7 
2.3  Discrete-time (DT) ΔΣ ADCs ..........................................................................10 
2.4  Continuous-time (CT) ΔΣ ADCs .....................................................................13 
3.  Problem Statement and Review of Previous Works ................................................. 20 
3.1  Excess Loop Delay ..............................................................................................20 
3.2  Early Compensation Methods .............................................................................22 
3.2.1  DAC Pulse Selection................................................................................... 22 
3.2.2  Feedback Coefficient Tuning ...................................................................... 24 
3.2.3  Additional Feedback Parameters ................................................................ 25 
4.  Model Matching Compensation Method algorithm .................................................. 27
LIST OF CONTENTS (Continued)

Page
4.1  Control Theory Review .......................................................................................27 
4.2  Pole-Placement Control ......................................................................................30 
4.3  Model Matching Control .....................................................................................33 
4.4  Compensation Solution to Excess Loop Delay ...................................................38 
5.  Proposed Design Performance Evaluation ................................................................ 53 
5.1  Simulation Setup and Results .............................................................................54 
5.2  Applicability Discussion .....................................................................................57 
5.2.1  In-band noise power .................................................................................... 57 
5.2.2  Output noise power spectrum ..................................................................... 59 
5.2.3  Output power spectrum ............................................................................... 62 
 0.7
5.3  Based Model Matching Experiment Results .....................................65 
d
6.  Summary and Conclusion ......................................................................................... 69 
7.  Bibliography ............................................................................................................. 71
LIST OF FIGURES

Figure Page
Figure 1.1 General CT ΔΣ ADCs .................................................................................... 2 
Figure 1.2 Practical CT ΔΣ ADCs ................................................................................... 2 
Figure 2.1 The general DSP system with both ADC and DAC converters ........................ 5 
Figure 2.2. N-bit Resistor-String DAC ............................................................................... 6 
Figure 2.3 General ΔΣ oversampling ADC structure ...................................................... 7 
Figure 2.4 (a) Relationship between input and output of a quantizer (b) relationship
between quantization noise and quantizer input of a 4-level quantizer .............................. 8 
Figure 2.5 A First order ΔΣ Modulator............................................................................ 9 
Figure 2.6 Linear z-domain ΔΣ ADC model ................................................................. 11 
Figure 2.7 A Second-order ΔΣ Modulator ..................................................................... 13 
Figure 2.8(a) Discrete-Time ΔΣ Modulator ................................................................... 14 
Figure 2.8(b) Continuous-Time ΔΣ Modulator ............................................................. 14 
Figure 2.9 Closed and open-loop CT ΔΣ ADCs and its DT equivalence form ............. 16 
Figure 2.10 Common DAC pulse types: (a) NRZ, (b) RZ (c) HRZ ................................. 17 
Figure 2.11 Block diagram of the second-order LP CT ΔΣ ADC ................................. 19 
Figure 4.2 Open-loop control system configuration ......................................................... 28 
Figure 4.3 Close-loop control system configuration with one degree of freedom ........... 29 
Figure 4.4 Close-loop control system configuration with two degrees of freedom .......... 29
LIST OF FIGURES (Continued)

Figure Page
Figure 4.5 General CT ΔΣ ADC block diagram ............................................................ 38 
Figure 4.6 Practical CT ΔΣ ADC block diagram ........................................................... 39 
Figure 4.7 An equivalent DT block diagram from Figure 4.6 .......................................... 40 
Figure 4.8 Linearized model of DT equivalent block diagram ......................................... 41 
Figure 4.10 Equivalent linearized block diagram with two compensators ....................... 43 
Figure 5.1 CT ΔΣ ADC in MATLAB Simulink ............................................................ 53 
Figure 5.2 Zero delay output power spectrum with SQNR=84dB ................................... 54 
Figure 5.3 Output Power Spectrum when  0.5 .......................................................... 55 
d
Figure 5.4 CT ΔΣ ADC block diagram with compensators C and C ......................... 55 
1 2
Figure 5.5 Output power spectrum with compensators when  0.5 ............................ 56 
d
Figure 5.7 Output noise power spectrum from  0to  0.8 without compensation61 
d d
Figure 5.8 Output noise power spectrum from  0to  0.8 with compensation .... 62 
d d
Figure 5.9 Output power spectrum when  0,0.2,0.4,0.6,0.8 without compensation 63 
d
Figure 5.10 Output power spectrum when  0,0.2,0.4,0.6,0.8 with compensation ... 64 
d
Figure 5.11 Output power spectrum when  0,0.2,0.4,0.6,0.8with 0.7 based algorithm
d
........................................................................................................................................... 67
LIST OF TABLES

Table Page
Table 4.1 Poles and Zeros of STF based on different value of  ................................... 42 
d
Table 5.1 SQNR with different values of  both with and without compensation ........ 65 
d
Table 5.2 SQNR with 0.5 and  0.7based algorithms ........................................ 68 
d d