CMOS-MEMS Enhanced Power Amplifiers

220 Pages·2012·6.48 MB·English

by  Leon Wang

CMOS-MEMS Enhanced Power Amplifiers

Submitted in partial fulfillment of the requirements for

the degree of

Doctor of Philosophy

in

Electrical & Computer Engineering

Leon S. Wang

B.S., Electrical Engineering and Computer Sciences, UC Berkeley
M.S., Electrical & Computer Engineering, Carnegie Mellon University

Carnegie Mellon University
Pittsburgh, PA

May, 2011
© Leon S. Wang 2011
All rights reserved

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To my parents

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Abstract
CMOS-MEMS post-processing allows for the monolithic integration of CMOS and
MEMS without any additional lithography masks and creates opportunities for circuits that can
take advantage of such integration. This thesis explores the enhancement of power amplifiers by
the CMOS-MEMS post-process. Below 5 GHz, there is an abundance of wireless standards and a
frequency-reconfigurable power amplifier would be useful for multi-band radios. Such a power
amplifier can take advantage of a CMOS-MEMS variable capacitor with certain advantages over
switched capacitors and MOS/diode varactors to enable this frequency reconfigurability, and this
thesis demonstrates such a power amplifier that is tunable from 3.4 GHz to 4.8 GHz and also
integrates an LC balun. This power amplifier is capable of delivering 18.18 to 19.88 dBm of
power across the frequency range with a maximum PAE of 17.72%. Compared to other power
amplifiers in 0.35-μm CMOS, this power amplifier operates at a higher frequency and is also
frequency-reconfigurable. Above 20 GHz, the dominant concern for a power amplifier is no
longer being capable of operating in different frequency bands but rather power efficiency
because gain and power are hard to come by at these frequencies. A 26 GHz 4-way Wilkinson
power combiner employing micromachined coplanar waveguide transmission lines with the
substrate removed by the CMOS-MEMS post-process to reduce loss is proposed and
demonstrated in this thesis. Without the resistor isolation network, the 4- way power combiner
has 0.4 dB of insertion loss with the pads, and 0.34 dB of insertion loss without the pads. All the
circuits in this thesis were fabricated in Jazz Semiconductor‘s 0.35 μm process and subsequently
processed by the CMOS-MEMS post-process.

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Acknowledgements
First and most importantly, I would like to acknowledge my advisor, Dr. Tamal
Mukherjee. One of the things I have yet to understand in life is why anyone would want to be a
professor, invest 4 or 5 years of time to transform a graduate student who knows next to nothing
into someone capable of performing professional research, watch that graduate student graduate,
and then repeat the process with other graduate students over and over again. With this thought
in mind, I am very grateful for his time in advising me, especially for his attempt to have
meetings with me every week in order to ensure my progress. Although there have been ups and
downs over the course of the Ph.D., with my advisor‘s steady hand, somehow things worked out
in the end. I would also like to thank the members of my Ph.D. committee, Professor Richard L.
Carley, Professor Jeyanandh Paramesh, and Dr. Hasnain Lakdawala for their advice on what
direction I should pursue.
I would also like to acknowledge several individuals for their help. Abhishek Jajoo was
the senior graduate student I often turned to for help and I am grateful for our discussions. John
Reinke‘s work on a CMOS-MEMS variable capacitor was critical to the success of my own
work and he was also very instrumental in churning out papers as well as writing the project
reports that won us 3rd place in phase I and II of the 2007/2008 SRC/SIA Design Challenge
along with Abhishek Jajoo, Dr. Tamal Mukherjee, and Dr. Gary K. Fedder. John Reinke also
took several SEM pictures for me and I am thankful for that. Yu-Jen (Dylan) Fang spent a good
number of days wirebonding one of my chips with a buggy wirebonder, and without his help I
would not have been able to test one of my chips. Suresh Santhanam post-processed my chips
and I am very thankful for his work because I did not have to go into the cleanroom.
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I would also like to acknowledge other officemates I have not yet mentioned for putting
up with my goofing off in the office: Nathan Lazarus, Kristen Dorsey, Phillip Bergeron, Peter
Gilgunn, Amy Wung, Congzhong Guo, Jonathan Rotner, Louis Draghi, Jie Wang, Fernando
Alfaro, and Byung Woo Yoon.
There are also certain individuals from before my time at Carnegie Mellon University
that I would like to acknowledge. I would like to thank former UC Berkeley graduate student
Simone Gambini for giving me the opportunity to do layout for him when I was an
undergraduate. I am very grateful to former supervisors Tom Kwan and Sumant Ranganathan
from Broadcom, San Jose, CA for a summer internship from which I gained a very useful
tapeout experience which would later help me in graduate school. Andreas Fischer from Lam
Research Corporation suggested that I pursue a Ph.D. instead of stopping with a Master‘s and I
am glad I took his advice.
I would also like to thank my parents, Chunsing and Esther Wang for their love and
support. I tend to be reserved with emotions and I probably don‘t tell him how much I love them
as much as I should so hopefully I can make up for some of that here.
This work was funded by The Center for Circuit & System Solutions (C2S2), The
Industrial Technology Research Institute (ITRI) Labs @ CMU, and National Science Foundation
(NSF) proposal CCR-0325344.

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Table of Contents
Abstract ................................................................................................................................ iv
Acknowledgements ........................................................................................................................v
Table of Contents ........................................................................................................................ vii
List of Figures ............................................................................................................................. xiii
List of Tables ............................................................................................................................ xxvi
Chapter 1 Introduction ............................................................................................................1
1.1 Introduction ..............................................................................................................1
1.2 Motivation ................................................................................................................4
1.3 Thesis contributions .................................................................................................6
1.4 Thesis outline ...........................................................................................................6
1.5 References ................................................................................................................7
Chapter 2 Background on frequency-reconfigurable power amplifiers .............................9
2.1 Introduction ..............................................................................................................9
2.2 Tunable capacitors ...................................................................................................9
2.2.1 MOS varactors .............................................................................................9
2.2.2 Diode varactors ..........................................................................................14
2.2.3 Switched capacitors ...................................................................................16
2.2.4 CMOS-MEMS variable capacitor ..............................................................21
2.2.5 Comparison of tunable elements ................................................................23
2.3 References ..............................................................................................................24
Chapter 3 Background on power combining power amplifiers.........................................26
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3.1 Introduction ............................................................................................................26
3.2 Power combining techniques .................................................................................26
3.2.1 LC balun.....................................................................................................26
3.2.2 Transformer based power combiners .........................................................27
3.2.3 Distributed Wilkinson power combiner .....................................................30
3.2.4 Lumped Wilkinson power combiner .........................................................32
3.3 Summary ................................................................................................................34
3.4 References ..............................................................................................................35
Chapter 4 Frequency-Reconfigurable Class E PA ..............................................................36
4.1 Introduction ............................................................................................................36
4.2 Class E background................................................................................................36
4.3 Frequency-Reconfigurable Class E Theory ...........................................................39
4.4 Design ....................................................................................................................41
4.5 Measurement Results .............................................................................................45
4.6 Potential improvements for the PA ........................................................................49
4.6.1 The ground path .........................................................................................49
4.6.2 The V line ...............................................................................................50
DD
4.6.3 Modeling of critical parasitics ...................................................................51
4.6.4 Area can be used more wisely ...................................................................52
4.6.5 New comparison between measured and simulated results .......................52
4.7 Summary ................................................................................................................53
4.8 References ..............................................................................................................54
Chapter 5 Frequency-Reconfigurable Class E PA with a CMOS-MEMS LC Balun .....56
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5.1 Introduction ............................................................................................................56
5.2 Design ....................................................................................................................56
5.2.1 Choice of variable capacitors .....................................................................56
5.2.2 Power combiner .........................................................................................57
5.2.3 Circuit topology explained .........................................................................58
5.2.4 Effect of the LC balun approximation .......................................................62
5.2.5 Performance penalty of the LC balun approximation ................................69
5.2.6 A-to-D converter for capacitor array control .............................................73
5.3 Improvements over the previous power amplifier .................................................75
5.3.1 Solving the ground issue ............................................................................75
5.3.2 Solving the V issue ................................................................................76
DD
5.3.3 Modeling issues .........................................................................................77
5.3.4 Area was used more wisely........................................................................78
5.4 Measurement Results .............................................................................................78
5.4.1 Testing details ............................................................................................78
5.4.2 Capacitor sweep summary .........................................................................80
5.4.3 Input power sweep summary .....................................................................88
5.4.4 Second stage gate bias summary ................................................................92
5.5 Analysis of Results ................................................................................................93
5.6 Use as an Antenna Mismatch Compensator ..........................................................99
5.6.1 Testing details ............................................................................................99
5.6.2 Measurement results ................................................................................102
5.6.3 Comparison with simulation ....................................................................104
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5.6.4 Analysis....................................................................................................106
5.7 Summary ..............................................................................................................107
5.8 References ............................................................................................................108
Chapter 6 CMOS-MEMS Power Combiner......................................................................110
6.1 Introduction ..........................................................................................................110
6.2 Design ..................................................................................................................111
6.2.1 CMOS-MEMS transmission line .............................................................111
6.2.2 Combining/splitting node.........................................................................118
6.2.3 Resistor Isolation network .......................................................................121
6.3 Measurement Results ...........................................................................................122
6.3.1 Testing details ......................................................................................................122
6.3.2 Measured S-parameters ........................................................................................124
6.3.3 Measurement discussion ......................................................................................126
6.4 Resistor isolation network non-idealities .............................................................129
6.5 Comparison with alternatives ..............................................................................130
6.5.1 Comparison with literature ......................................................................130
6.5.2 Lumped Wilkinson vs. Distributed Wilkinson ........................................131
6.5.3 CMOS-MEMS transmission line vs. CMOS-MEMS inductor................134
6.5.4 CMOS-MEMS transmission line vs. slotted shield transmission line .....141
6.5.5 Distributed Wilkinson vs. Transformer-Based Power Combiner ............143
6.6 50 Ω characteristic impedance CMOS-MEMS transmission line .......................145
6.7 Summary ..............................................................................................................147
6.8 References ............................................................................................................148
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