CMOS Low-Noise Amplifier Design for Reconfigurable Mobile Terminals

137 Pages·2005·1.1 MB·English

CMOS Low-Noise Amplifier Design
for Reconfigurable Mobile Terminals
vorgelegt von
Diplom-Ingenieur
Dariusz Pien´kowski
Von der Fakult¨at IV Elektrotechnik und Informatik
der Technishen Universit¨at Berlin
zur Verleihung des akademischen Grades
Doktor der Ingenieurwissenschaften
— Dr-Ing. —
genehmigte Dissertation
Promotionsausschuss:
Vorsitzender: Prof. Dr. Ing. H. Klar
Gutachter: Prof. Dr. Ing. G. B¨ock
Gutachter: Prof. Dr. Ing. P. Weger
Tag der wissenschaftlichen Aussprache: 03. Dez. 2004
Berlin 2004
D 83
Copyright c 2004 by Dariusz Pien´kowski
(cid:13)
All rights reserved
Abstract
Communication standards developed in Europe, Japan and USA are not
compatible with each other. This is a profound drawback particularly
in the digital cellular telephony, where there is no common standard up to
now.
The variety of wireless standards leads to some disadvantages, therefore
the need for reconfigurability seems to be evident. A reconfigurable terminal
should be able to support different standards.
Reasonable integration of different standards may include standards,
which belong to the same family (e.g., GSM), but are developed in different
continents. Such terminals have been already produced and a broad offer
exists on the market.
A rather new approach of the standard integration is the combination
of different families of standards, for example between wireless data and
digital cellular telephony like UMTS with WLAN or HIPERLAN. In this
case, nearly all parameters defining a standard are different.
In the scope of this work the multistandard, reconfigurable terminal is
considered that supports the OFDM based WLAN standards (IEEE802.11
and Hiperlan/2) and the CDMA based UMTS FDD standard. Special con-
sideration has been made for the receiver of this terminal.
A reconfigurable hybrid architecture has been developed, rather than an
architecture using many parallel switchable transceivers. Additionally to the
hybrid architecture, a study on RF impairments is given.
The second part of this work handles with transistor physics and low
noise amplifier design for a reconfigurable receiver, defined earlier. Since the
smallFETsizesofstateoftheartsub-micronRF-MOS-technologieshavelow
capacitance values, thus large inductors are needed for matching. Because
of theirs large dimensions they are placed off-chip. For this reason, the pad
capacitance can not be longer neglected in the design process. It is shown
II Abstract
that the noise figure of low-noise amplifiers can be improved considerably
by a proper choice of passive components. A design methodology is intro-
duced, which reduces the equivalent noise resistance, and thus very good
noise performance can be achieved in spite of rather poor noise matching.
The measurements of the amplifier, in respect to the noise performance
and power consumption, show very good results, one of the best ever re-
ported. 0.76 dB noise figure and 12 dB gain were achieved at 2.14 GHz,
3.5 mA supply current and 1.2 V supply voltage.
Acknowledgments
I would like to thank my doctoral thesis supervisor Professor Georg B¨ock
for his continuously support and many ideas that help me with work on
this thesis.
IwishtoacknowledgealsoNokiaResearchCenterBochum,Germany. For
the last three years, I have worked together with the Nokia Research Center,
within the German funded BMBF-project “Software Defined Radio Based
Architecture Studies for Reconfigurable Mobile Communication Systems”
(RMS), No. 01 BU171. This thesis is partially based on the research carried
out during this cooperation.
I also would like to thank my parents. Without their support in all aspect
of my life, this thesis would never come true. I owe many very important
things in my life to my parents, therefore I regret that my father had died
before I have finished this thesis.
Finally I would like to thank my wife, Joanna for invaluable help and
support. She has cheered me up during work on this thesis and during the
long time of our separation, when every two weeks I travelled between Berlin
and Warsaw back and forth. Actually, she has made almost all graphics in
this thesis.
I can not forgot also my little daughter, Agata. Although unconscious
of all the matter, she has also participated in writing this thesis. With his
calmness, she let his father to go to sleep in the night. Therefore, I could
finish faster this work. It is time now, to repay her for that.
This work is dedicated to her.

Contents
Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
Acknowledgments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III
Chapter 1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1. Scope of This Work . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Chapter 2. Reconfigurable Systems . . . . . . . . . . . . . . . . . . . 5
2.1. General Concepts in Multi-standard Radios . . . . . . . . . . . . . 6
2.1.1. One-Bit Reconfiguration . . . . . . . . . . . . . . . . . . . . 6
2.1.2. Software Defined Radio . . . . . . . . . . . . . . . . . . . . 8
2.1.3. Software Reconfigurable Radio . . . . . . . . . . . . . . . . 8
2.2. RF Receiver Requirements . . . . . . . . . . . . . . . . . . . . . . . 8
2.2.1. UMTS FDD . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2.2. WLAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.3. Reconfigurable RF Receiver Architecture . . . . . . . . . . . . . . . 16
2.4. LNA Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.5. RF Related Impairments . . . . . . . . . . . . . . . . . . . . . . . . 22
2.5.1. Frequency Offset . . . . . . . . . . . . . . . . . . . . . . . . 24
2.5.2. Phase Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.5.3. Direct Current Offset . . . . . . . . . . . . . . . . . . . . . . 26
2.5.4. I/Q Imbalance . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.5.5. Nonlinearities . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Chapter 3. Passive Devices . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.1. Inductors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.1.1. Spiral Inductors . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.1.2. Bond-wire Inductors . . . . . . . . . . . . . . . . . . . . . . 36
3.2. MIM Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.3. Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.4. Pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
VI Contents
Chapter 4. RF MOSFET Devices . . . . . . . . . . . . . . . . . . . . . 41
4.1. Long-channel Regime . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.2. Short-channel Regime . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.2.1. Velocity Saturation . . . . . . . . . . . . . . . . . . . . . . . 43
4.2.2. Threshold Reduction . . . . . . . . . . . . . . . . . . . . . . 44
4.2.3. Hot Carriers . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.3. Radio Frequency Operation . . . . . . . . . . . . . . . . . . . . . . 45
4.3.1. MOSFET Capacitances . . . . . . . . . . . . . . . . . . . . 45
4.3.2. Distributed Gate Resistance . . . . . . . . . . . . . . . . . . 46
4.3.3. Channel Resistance and Transit Time Effects . . . . . . . . 48
4.3.4. Small-signal RF-model . . . . . . . . . . . . . . . . . . . . . 50
4.3.5. Noise Model of a MOSFET . . . . . . . . . . . . . . . . . . 50
4.3.6. Noise Matching . . . . . . . . . . . . . . . . . . . . . . . . . 53
Chapter 5. Noisy two-ports. . . . . . . . . . . . . . . . . . . . . . . . . 57
5.1. Noise Representation of Noisy Circuits . . . . . . . . . . . . . . . . 57
5.2. Correlation Matrices of Noisy Two-ports . . . . . . . . . . . . . . . 60
5.3. Relations Between Different Noise Correlation Matrices . . . . . . . 62
5.4. Relations Between Different Electrical Matrices . . . . . . . . . . . 63
5.5. Interconnections of Noisy Two-ports . . . . . . . . . . . . . . . . . 63
Chapter 6. Low Noise Amplifier Design . . . . . . . . . . . . . . . . . 67
6.1. Impact of Channel and Gate Resistance on LNA Performance . . . 72
6.2. Choosing Transistor Width and Bias Conditions . . . . . . . . . . . 72
6.3. Two-port Noise Theory in LNA Design . . . . . . . . . . . . . . . . 81
6.3.1. Influence of source degeneration . . . . . . . . . . . . . . . . 81
6.3.2. Influence of Pad Capacitance with On-chip Inductance . . . 83
6.3.3. Influence of Pad Capacitance and Off-chip Inductance . . . 85
6.3.4. Comparison of two input matching principle . . . . . . . . . 87
6.3.5. Influence of On-chip Enhanced Inductance . . . . . . . . . . 88
6.4. Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Chapter 7. LNA Measurements . . . . . . . . . . . . . . . . . . . . . . 93
7.1. Measurement Test Bench . . . . . . . . . . . . . . . . . . . . . . . . 93
7.2. DC Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
7.3. S-parameter Measurements . . . . . . . . . . . . . . . . . . . . . . . 96
7.4. Noise Figure Measurements . . . . . . . . . . . . . . . . . . . . . . 99
7.5. Compression Measurements . . . . . . . . . . . . . . . . . . . . . . 103
7.6. Comparison with State-of-the-art Amplifiers . . . . . . . . . . . . . 103
Chapter 8. Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Contents VII
Appendix A. Cascode Amplifier. . . . . . . . . . . . . . . . . . . . . . 107
Appendix B. Electrical Chain Matrix of Cascode Amplifier . . . . 109
Appendix C. Simultaneously Power and Noise Matching in LNA 111
Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127