CMOS analog transmission gate design

150 Pages·2016·2.32 MB·English

by  Cynthia S. Bell

Rochester Institute of Technology
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6-1-1986
CMOS analog transmission gate design
Cynthia S. Bell
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CMOS ANALOG TRANSMISSION GATE DESIGN
by
Cynthia S. Bell
A Thesis Submitted
in
Partial Fulfillment
of the
Requirements for the Degree of
MASTER OF SCIENCE
in
Electrical Engineering
Approved by:
_Ly .::.-n_n_F_e _Fu _I_1e _r_ _
Prof.
._N_a_m_e_lIl_e-=g~ib_le_ __
Prof
._N_a_m_e_lIl_e-=g~ib_le_ __
Prof
Prof. ___________________________ _
DEPARTMENT OF ELECTRICAL ENGINEERING
COLLEGE OF ENGINEERING
ROCHESTER INSTITUTE OF TECHNOLOGY
ROCHESTER, NEW YORK
JUNE, 1986
~J~ Tmtls.OIt~'7i\ &w.l~§~
CMOS
Title of Theda
C__y_ n__ t_h_ia_S_u_e_B_e_II_ _______ bereb~.
I __ (grant,
deny) permission to the Wallace Memorial L1braryl of R.I'-T. , to
,
reproduce my thesis in whole or in part. Any reproduction will
not be tor commercial use or profit.
-XI-
ABSTRACT
CMOS technology has provided an integrated circuit equivalent for
the conventional electromechanical switch: the transmission gate.
CMOS analog transmission gates degrade signals passed through them
with noise due to gate clock feedthrough transients. A SPICE
parameter model for the Eastman Kodak CMOS process has been
developed and timing requirements for feedthrough cancellation in
typically structured transmission gate devices have been studied.
An alternate device structure for improved performance is
proposed.
-iii-
TABLE OF CONTENTS
Page
LIST OF FIGURES iv
LIST OF TABLES V
LIST OF SYMBOLS vi
INTRODUCTION 1
BACKGROUND & THEORY 2
DISCUSSION
A. Transmission Gate Test Structure Evaluation 12
B. Transistor Evaluation 17
1 Experimental Procedures
.
a. I-V Test Procedures 18
b. gjj Test Procedures 19
c . VT , 7 Test Procedures . . 20
2. Modified Gate and Channel Transistor Evaluation 22
3. CMOS Process Characterization Measurements 24
RESULTS
A CMOS Process Parameters 29
.
B. Transmission Gate Model and Timing Requirements 33
C. Proposed Structure for Improved Performance 39
CONCLUSIONS 41
APPENDIX A - Modified Gate and Channel Transistor Data
APPENDIX B - CMOS Process Characterization Transistor Data
APPENDIX C - Parameter Extraction Calculations
APPENDIX D - Gate Clock Timing SPICE Simulations
-iv-
LIST OF FIGURES
Figure 1 Simple FET Switch 2
.
Figure 2. Improved Switch 4
Figure 3. Improved Switch Cross-Section 5
Figure 4. Schematic Transmission Gate 6
Figure 5. Clock-Phase Controller 8
Figure 6. Circular Pass Transistor 8
Figure 7. Ron vs. Vin 9
Figure 8 Transmission Gate Leakage Model 10
.
Figure 9 Alternative Transmission Gate 10
.
Figure 10. Transmission Gate Test Structure 13
Figure 11. P- and n-channel Ron Vs . Vin 14
Figure 12. Transmission gate Ron vs. Vin vs. VG 14
Figure 13. Asymmetrical Clock Circuit 16
Figure 14. Drain Voltage and P Gate Clock 17
Figure 15. Drain Voltage and N Gate Clock 17
Figure 16. Typical I-V curve 19
Figure 17. Typical gM curve 21
Figure 18. Typical VT J curve 21
,
Figure 19. Flared Buried Channel FET 22
Figure 20. Segmented Drain FET 23
Figure 21. Photomicrograph of Segmented Drain Device 24
Figure 22. Die Position vs. VT 26
Figure 23. I-V Curve: Model and Data T2 6u 31
Figure 24. I-V Curve: Model and Data T2 80u 31
-v-
Figure 25. I-V Curve: Model and Data T4 6u 32
Figure 26. I-V Curve: Model and Data T4 80u 32
Figure 27. SPICE Transmission Gate Circuit Model 33
Figure 28 . Model of N-channel Transient 35
Figure 29 . Model of P-channel Transient 35
Figure 30. Model with Misaligned Gate Clocks 36
Figure 31. Model with Aligned Gate Clocks 36
Figure 32. Model with Retarded N-channel Clock Slope 37
Figure 33. Model with .03 Nanosecond N-channel Clock Lag.. 37
Figure 34. Model with .04 Nanosecond N-channel Clock Lag.. 38
Figure 35. Model with .05 Nanosecond N-channel Clock Lag.. 38
Figure 36. New Transmission Gate Structure 40
LIST OF TABLES
Table 1. Resistance Variation with Gate Voltage 15
Table 2. Resistance Variation with Device Width 15
Table 3. Agreement of Simulated and Measured I-V Curves... 29
Table 4. SPICE Parameters for CMOS Process 30
-VI-
LIST OF SYMBOLS
Symbol Definition, units
Nsub Substrate (or tub) dopant concentration, atoms/cm3
ni Intrinsic carrier concentration, atoms/cm3
Permittivity, Farads/meter
t Thickness, meters
*f Fermi potential
U Micron (10-6 meters)
P Mobility, centimeters2/Volt-second
W Device channel width, meters
L Device channel length, meters
7 Body effect factor
A Channel length modulation factor
vG Gate voltage, Volts
vD Drain voltage, Volts
vs Source voltage. Volts
Vin Input (signal) voltage. Volts
VT Threshold voltage. Volts
VT0 Zero bias threshold voltage, Volts
Q Resistance, Ohms
K Boltzmann's constant, 1.38*1023 Joules/0 Kelvin
Kilo (103)
vk
T Temperature, Kelvin
q Charge, Coulombs
ys MOSFET gain factor
INTRODUCTION
CMOS technology has provided an integrated circuit equivalent for
the conventional electromechanical switch: the transmission gate.
The use of transmission gates can lead to more efficient layouts
and can reduce logic, thus reducing die size and improving circuit
speed. This gate is often used to multiplex signals into analog-
to-digital converters, to tristate lines, and to isolate sections
of circuits. The transmission gate has become a major building
block for logic design, data filtering, data conversion, and other
signal processing circuits.
Transmission gates can benefit many functions, but they have
limitations which are a result of their resistive nature. They
have no drive capability of their own. An ideal semiconductor
switch would have infinite off-resistance, zero on-resistance , no
leakage, no parasitic capacitance, and would consume no power.
Since the transmission gate is not ideal, the integrated circuit
designer must optimize performance by using the switch
configuration that most closely meets circuit requirements. In
this work, emphasis is placed on transmission gates which rapidly
switch small signals with minimum signal distortion. Further, a
transmission gate configuration suitable for the CMOS process at
the Eastman Kodak Company is sought .
2 -
BACKGROUND AND THEORY
The simplest switch implementation is a pass transistor, such as
the Field Effect Transistor (FET) shown in figure 1. FET switches
can be used to transfer voltage to nodes with large impedances, to
switch currents between two alternative loops, or to transfer
charge, as with switched capacitor filters, where charge is
conserved.
^
l
1
<R
Figure 1. Simple FET Switch
The signal at the output, Vout
,
Vout = IdR (D
depends on the current through the device, ID
,
iDsat = ;8(Vgs - VT)2 (2a)
where JS is composed of the fabrication and geometrical parameters,
= //OXW / 2toxL( 1 + AVDS) (2b)
With the appropriate biases, the voltage on the gate of the device,
VGS, controls the blockage or passage of signals.
This switch implementation has three important limitations. The
first is a result of the requirement for conduction: the voltage