CMOS analog integrated circuits : high-speed and power-efficient design

914 Pages·2011·6.16 MB·English

by  Tertulien Ndjountche

ElEctrical EnginEEring
Ndjountche
CMOS AnAlOg
CMOS Analog
I
IntegrAted
Integrated Circuits
n
HigH-Speed and power-efficient deSign t
CIrCuItS
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High-speed and power-efficient analog integrated circuits can be used as standalone C
devices or to interface modern digital signal processors and micro-controllers in various g
applications, including multimedia, communication, instrumentation, and control M
systems. New circuit architectures and the ever-decreasing size of complementary metal
r
oxide semiconductor (CMOS) transistors have accelerated the trend toward system-
HigH-Speed and power-efficient deSign
on-a-chip design, which merges analog circuits with digital components onto a single O
A
chip. CMOS Analog Integrated Circuits: High-Speed and Power-Efficient Design
describes the important aspects in designing these analog circuits and provides a S
t
comprehensive and in-depth examination of design techniques and circuit architectures, φ φ
2 C 2
emphasizing practical aspects of integrated circuit implementations.
e
A
φ φ
Focusing on designing and verifying analog integrated circuits, the author reviews φ C 1 C 1
d + − 2 1
design techniques for important components such as amplifiers, comparators, and Vy1 Vy1
n
multipliers. The book details all aspects, from specifications to the final chip, of the φ
development and implementation process of continuous-time and switched-capacitor V+ V1+ 1 C 1 −+ V+
x1 0
C φ
filters, analog-to-digital converters (ADCs), digital-to-analog converters (DACs), A 1 C 1
phase-locked loops (PLLs), and delay-locked loops (DLLs). It addresses performance Vx−1 − +− V0−
V φ
limitation issues affecting the operation of an analog circuit at the architecture and I l 1 2 C 1 φ1 C φ1
transistor levels, along with conceptual and practical solutions to problems that can r
arise in the design process. O φ φ φ
C Vy+N Vy−N 2 C N 2 C 2
This comprehensive and illustrative book provides balanced coverage of theoretical and
φ
practical issues that will allow the reader to design CMOS analog integrated circuits g + VN+ 1 C N
u VxN
with improved electrical performance. The chapters contain easy-to-follow mathematical φ
1 C N
derivations of all equations and formulas, graphical plots, and open-ended design −
V
problems to help determine the most suitable circuit architecture for a given set of It xN VN− φ2 C N
performance specifications. This practical text can serve as a valuable resource for
analog circuit designers and electrical engineering students with background knowledge
S
in basic microelectronics.
Tertulien Ndjountche
K12557
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K12557_Cover_mech.indd 1 4/12/11 10:27 AM
CMOS AnAlOg
IntegrAted
CIrCuItS
HigH-Speed and power-efficient deSign
K12557.indd 1 4/19/11 10:03:24 AM
TThhiiss ppaaggee iinntteennttiioonnaallllyy lleefftt bbllaannkk
CMOS AnAlOg
IntegrAted
CIrCuItS
HigH -Speed and p ower-e fficient deS ign
Tertulien Ndjountche
Boca Raton London New York
CRC Press is an imprint of the
Taylor & Francis Group, an informa business
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Contents
Preface xv
Content overview . . . . . . . . . . . . . . . . . . . . . . . . . . . xvii
Feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xx
Acknowledgments . . . . . . . . . . . . . . . . . . . . . . . . . . . xx
List of Figures xxiii
List of Tables li
1 Mixed-Signal Integrated Systems: Limitations and
Challenges 1
1.1 Integrated circuit design flow . . . . . . . . . . . . . . . . . . 2
1.2 Design technique issues . . . . . . . . . . . . . . . . . . . . . 6
1.3 Integrated system perspectives . . . . . . . . . . . . . . . . . 7
1.4 Built-in self-test structures . . . . . . . . . . . . . . . . . . . 8
1.5 Concluding remarks . . . . . . . . . . . . . . . . . . . . . . . 9
1.6 To probe further . . . . . . . . . . . . . . . . . . . . . . . . . 9
2 MOS Transistors 11
2.1 Transistor structure . . . . . . . . . . . . . . . . . . . . . . . 12
2.1.1 I/V characteristics of MOS transistors . . . . . . . . . 13
2.1.2 Drain current in the strong inversion approximation . 14
2.1.3 Drain current in the subthreshold region . . . . . . . . 17
2.1.4 MOS transistor capacitances . . . . . . . . . . . . . . 20
2.1.5 Scaling effects on MOS transistors . . . . . . . . . . . 21
2.2 Transistor SPICE models . . . . . . . . . . . . . . . . . . . . 23
2.2.1 Electrical characteristics . . . . . . . . . . . . . . . . . 23
2.2.2 Temperature effects . . . . . . . . . . . . . . . . . . . 27
2.2.3 Noise models . . . . . . . . . . . . . . . . . . . . . . . 28
2.3 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.4 Circuit design assessment . . . . . . . . . . . . . . . . . . . . 32
Bibliography 37
v
vi
3 Physical Design of MOS Integrated Circuits 39
3.1 MOS Transistors . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.2 Passive components . . . . . . . . . . . . . . . . . . . . . . . 41
3.2.1 Capacitors . . . . . . . . . . . . . . . . . . . . . . . . 42
3.2.2 Resistors . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.2.3 Inductors . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.3 Integrated-circuit (IC) interconnects . . . . . . . . . . . . . . 46
3.4 Physical design considerations . . . . . . . . . . . . . . . . . 48
3.5 IC packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.7 Circuit design assessment . . . . . . . . . . . . . . . . . . . . 53
Bibliography 57
4 Bias and Current Reference Circuits 59
4.1 Current mirrors . . . . . . . . . . . . . . . . . . . . . . . . . 60
4.1.1 Simple current mirror . . . . . . . . . . . . . . . . . . 60
4.1.2 Cascode current mirror . . . . . . . . . . . . . . . . . 62
4.1.3 Low-voltage active current mirror. . . . . . . . . . . . 75
4.2 Current and voltage references . . . . . . . . . . . . . . . . . 76
4.2.1 Supply-voltage independent current reference . . . . . 78
4.2.2 Bandgap references . . . . . . . . . . . . . . . . . . . . 79
4.2.2.1 Low-voltage bandgap voltage reference . . . 82
4.2.2.2 Curvature-compensated bandgap voltage
reference . . . . . . . . . . . . . . . . . . . . 83
4.2.3 Floating-gate voltage reference . . . . . . . . . . . . . 86
4.3 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
4.4 Circuit design assessment . . . . . . . . . . . . . . . . . . . . 87
Bibliography 93
5 CMOS Amplifiers 95
5.1 Differential amplifier . . . . . . . . . . . . . . . . . . . . . . . 96
5.1.1 Dynamic range . . . . . . . . . . . . . . . . . . . . . . 97
5.1.2 Source-coupled differential transistor pair . . . . . . . 99
5.1.3 Current mirror . . . . . . . . . . . . . . . . . . . . . . 101
5.1.4 Slew-rate limitation . . . . . . . . . . . . . . . . . . . 102
5.1.5 Small-signal characteristics . . . . . . . . . . . . . . . 103
5.1.6 Offset voltage . . . . . . . . . . . . . . . . . . . . . . . 108
5.1.7 Noise in a differential transistor pair . . . . . . . . . . 110
5.1.8 Operational amplifier . . . . . . . . . . . . . . . . . . 111
5.2 Linearization techniques for transconductors . . . . . . . . . 114
5.3 Single-stage amplifier . . . . . . . . . . . . . . . . . . . . . . 129
5.4 Folded-cascode amplifier . . . . . . . . . . . . . . . . . . . . 130
5.5 Fully differential amplifier architectures . . . . . . . . . . . . 135
5.5.1 Fully differential folded-cascode amplifier . . . . . . . 135
vii
5.5.1.1 Basic structure . . . . . . . . . . . . . . . . . 135
5.5.1.2 Gain-enhanced structure . . . . . . . . . . . 138
5.5.2 Telescopic amplifier . . . . . . . . . . . . . . . . . . . 143
5.5.3 Common-mode feedback circuits . . . . . . . . . . . . 146
5.5.3.1 Continuous-time common-mode feedback
circuit . . . . . . . . . . . . . . . . . . . . . . 146
5.5.3.2 Switched-capacitor common-mode feedback
circuit . . . . . . . . . . . . . . . . . . . . . . 150
5.5.4 Pseudo fully differential amplifier . . . . . . . . . . . . 154
5.6 Multi-stage amplifier structures . . . . . . . . . . . . . . . . 156
5.6.1 Output stage . . . . . . . . . . . . . . . . . . . . . . . 157
5.6.2 Two-stage amplifier . . . . . . . . . . . . . . . . . . . 167
5.6.3 Optimization of a two-pole amplifier for fast settling
response . . . . . . . . . . . . . . . . . . . . . . . . . . 174
5.6.4 Three-stage amplifier. . . . . . . . . . . . . . . . . . . 177
5.7 Rail-to-rail amplifiers . . . . . . . . . . . . . . . . . . . . . . 186
5.7.1 Amplifier with a class AB input stage . . . . . . . . . 187
5.7.2 Two-stage amplifier with class AB output stage . . . . 189
5.7.3 Amplifier with rail-to-rail input and output stages . . 190
5.8 Amplifier characterization . . . . . . . . . . . . . . . . . . . . 194
5.8.1 Finite gain and bandwidth . . . . . . . . . . . . . . . 194
5.8.2 Phase margin . . . . . . . . . . . . . . . . . . . . . . . 195
5.8.3 Input and output impedances . . . . . . . . . . . . . . 195
5.8.4 Power supply rejection . . . . . . . . . . . . . . . . . . 195
5.8.5 Slew rate . . . . . . . . . . . . . . . . . . . . . . . . . 195
5.8.6 Low-frequency noise and dc offset voltage . . . . . . . 196
5.8.6.1 Auto-zero compensation scheme . . . . . . . 198
5.8.6.2 Chopper technique . . . . . . . . . . . . . . . 201
5.9 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
5.10 Circuit design assessment . . . . . . . . . . . . . . . . . . . . 204
Bibliography 219
6 Nonlinear Analog Components 225
6.1 Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
6.1.1 Amplifier-based comparator . . . . . . . . . . . . . . . 226
6.1.2 Comparator using charge balancing techniques . . . . 233
6.1.3 Latched comparators . . . . . . . . . . . . . . . . . . . 234
6.1.3.1 Static comparator . . . . . . . . . . . . . . . 235
6.1.3.2 Dynamic comparator . . . . . . . . . . . . . 239
6.2 Multipliers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
6.2.1 Multiplier cores . . . . . . . . . . . . . . . . . . . . . . 244
6.2.1.1 Multiplier core based on externally controlled
transconductances . . . . . . . . . . . . . . . 244
viii
6.2.1.2 Multipliercorebasedonthequarter-square
technique . . . . . . . . . . . . . . . . . . . . 249
6.2.1.3 Design issues . . . . . . . . . . . . . . . . . . 255
6.2.2 Design examples . . . . . . . . . . . . . . . . . . . . . 256
6.3 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
6.4 Circuit design assessment . . . . . . . . . . . . . . . . . . . . 259
Bibliography 265
7 Continuous-Time Circuits 269
7.1 Wireless communication system . . . . . . . . . . . . . . . . 270
7.1.1 Receiver and transmitter architectures . . . . . . . . . 272
7.1.2 Frequency translation and quadrature multiplexing . . 275
7.1.3 Architecture of a harmonic-rejection transceiver. . . . 281
7.1.4 Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . 282
7.1.4.1 Power amplifier . . . . . . . . . . . . . . . . 283
7.1.4.2 Low-noise amplifier . . . . . . . . . . . . . . 292
7.1.5 Mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
7.1.6 Voltage-controlled oscillator . . . . . . . . . . . . . . . 306
7.1.7 Automatic gain control . . . . . . . . . . . . . . . . . 321
7.2 Continuous-time filters . . . . . . . . . . . . . . . . . . . . . 324
7.2.1 RC circuits . . . . . . . . . . . . . . . . . . . . . . . . 326
7.2.2 MOSFET-C circuits . . . . . . . . . . . . . . . . . . . 327
7.2.3 g -C circuits . . . . . . . . . . . . . . . . . . . . . . . 330
m
7.2.4 g -C operational amplifier (OA) circuits . . . . . . . . 331
m
7.2.5 Summer circuits . . . . . . . . . . . . . . . . . . . . . 335
7.2.6 Gyrator . . . . . . . . . . . . . . . . . . . . . . . . . . 336
7.3 Filter characterization . . . . . . . . . . . . . . . . . . . . . . 337
7.4 Filter design methods . . . . . . . . . . . . . . . . . . . . . . 338
7.4.1 First-order filter design . . . . . . . . . . . . . . . . . 340
7.4.2 Biquadratic filter design methods . . . . . . . . . . . . 342
7.4.2.1 Signal-flow graph-based design . . . . . . . . 342
7.4.2.2 Gyrator-based design . . . . . . . . . . . . . 346
7.4.3 Ladder filter design methods . . . . . . . . . . . . . . 349
7.4.3.1 LC ladder network-based design . . . . . . . 349
7.4.3.2 Signal-flow graph-based design . . . . . . . . 352
7.5 Design considerations for continuous-time filters . . . . . . . 356
7.5.1 Automatic on-chip tuning of continuous-time filters. . 356
7.5.2 Nonideal integrator . . . . . . . . . . . . . . . . . . . . 358
7.6 Frequency-control systems . . . . . . . . . . . . . . . . . . . 359
7.6.1 Phase-locked-loop-based technique . . . . . . . . . . . 359
7.6.1.1 Operation principle . . . . . . . . . . . . . . 359
7.6.1.2 Architecture of the master: VCO or VCF . . 360
7.6.1.3 Phase detector . . . . . . . . . . . . . . . . . 361
7.6.1.4 Implementation issues . . . . . . . . . . . . . 362
ix
7.6.2 Charge comparison-based technique . . . . . . . . . . 363
7.7 Quality-factor and bandwidth control systems . . . . . . . . 365
7.7.1 Magnitude-locked-loop-based technique . . . . . . . . 365
7.7.2 Envelope detection-based technique . . . . . . . . . . 366
7.8 Practical design considerations . . . . . . . . . . . . . . . . . 369
7.9 Other tuning strategies . . . . . . . . . . . . . . . . . . . . . 372
7.9.1 Tuning scheme using an external resistor . . . . . . . 372
7.9.2 Self-tuned filter . . . . . . . . . . . . . . . . . . . . . . 373
7.9.3 Tuning scheme based on adaptive filter technique . . . 375
7.10 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378
7.11 Circuit design assessment . . . . . . . . . . . . . . . . . . . . 378
Bibliography 395
8 Switched-Capacitor Circuits 403
8.1 Anti-aliasing filter . . . . . . . . . . . . . . . . . . . . . . . . 404
8.2 Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406
8.3 Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407
8.3.1 Switch description . . . . . . . . . . . . . . . . . . . . 407
8.3.2 Switch error sources . . . . . . . . . . . . . . . . . . . 409
8.3.3 Switch compensation techniques . . . . . . . . . . . . 413
8.4 Programmable capacitor arrays . . . . . . . . . . . . . . . . 414
8.5 Operational amplifiers . . . . . . . . . . . . . . . . . . . . . . 416
8.6 Track-and-hold (T/H) and sample-and-hold (S/H) circuits . 417
8.7 Switched-capacitor (SC) circuit principle . . . . . . . . . . . 425
8.8 SC filter design . . . . . . . . . . . . . . . . . . . . . . . . . . 430
8.8.1 First-order filter . . . . . . . . . . . . . . . . . . . . . 432
8.8.2 Biquad filter . . . . . . . . . . . . . . . . . . . . . . . 433
8.8.3 Ladder filter . . . . . . . . . . . . . . . . . . . . . . . 441
8.9 SC ladder filter based on the LDI transform . . . . . . . . . 441
8.10 SC ladder filter based on the bilinear transform . . . . . . . 449
8.10.1 RLC filter prototype-based design . . . . . . . . . . . 449
8.10.2 Transfer function-based design of allpass filters . . . . 456
8.11 Effects of the amplifier finite gain and bandwidth . . . . . . 459
8.11.1 Amplifier dc gain . . . . . . . . . . . . . . . . . . . . . 461
8.11.2 Amplifier finite bandwidth. . . . . . . . . . . . . . . . 463
8.11.2.1 Inverting integrator . . . . . . . . . . . . . . 463
8.11.2.2 Noninverting integrator . . . . . . . . . . . . 465
8.12 Settling time in the integrator . . . . . . . . . . . . . . . . . 466
8.13 Amplifier dc offset voltage limitations . . . . . . . . . . . . . 469
8.14 Computer-aided analysis of SC circuits . . . . . . . . . . . . 469
8.15 T/H and S/H circuits based on SC circuit principle . . . . . 473
8.16 Circuit structures with low sensitivity to nonidealities . . . . 478
8.16.1 Integrators . . . . . . . . . . . . . . . . . . . . . . . . 479
8.16.2 Gain stages . . . . . . . . . . . . . . . . . . . . . . . . 485