CMOS Analog Integrated Circuit Design Techniques for Low

119 Pages·2008·3.75 MB·English

CMOS Analog Integrated Circuit
Design Te chniques for
L o w - P o w e r e d U b i q u i t o u s D e v i c e

February 2008

Waseda University
Graduate School of Information, Production and Systems
Major in Information, Production and Systems Engineering

LSI Design Technologies

Jun Pan

Abstract
CMOS Analog Integrated Circuit Design Techniques
for Low-Powered Ubiquitous Device
Jun PAN
With the continuously expanding of market for ubiquitous devices such as wireless
sensor nodes, portable devices, and implantable medical devices, low-power design
is becoming a critical priority in integrated circuit design. Low-power design can
increase lifetime and/or achieve a smaller size. Therefore, one of the focuses of this
dissertation is to improve the low-power design techniques.
On the other hand, the advancement in low-power design makes it possible that
ubiquitous device can be powered by low-power energy source such as ambient energy
or small size batteries. In many well supplied devices the problem related to power
is essentially related to cost. However for low-powered devices the problem of power
is not only economics but also becomes very essential in terms of functionality. Due
to the usual very small amount of energy or unstable energy available the way the
engineer manages power becomes a key point in this area. Therefore, another focus
of this dissertation is to try finding ways to improve the power management problem.
Complementary metal oxide-semiconductor (CMOS) has become the predomi-
nant technology in integrated circuit design due to its high density, power savings
and low manufacturing costs. The whole integrated circuit industry will still continue
to benefit from the geometric downsizing that comes with every new generation of
semiconductor manufacturing processes. Therefore, only several CMOS analog inte-
grated circuit design techniques are proposed for low-powered ubiquitous device in
this dissertation.
In the first chapter, the motivations and the backgrounds of this dissertation are

presented.
In the second chapter, the first key cell circuit, a low-power sub-1-V self-biased
low-voltage reference, is proposed for low-power electronic applications based onbody
effect. A voltage reference with low sensitivity to the temperature and supply voltage
is one of the key issues in analog circuit design for ubiquitous device. A metal-oxide-
semiconductor field effect transistor (MOSFET) can beoperated at a lower voltage by
forward-biasing the source-substrate junction. This approach has been investigated
in detail and used to design an ultra-low power CMOS voltage reference for operation
at sub-1 V. The issues of CMOS latchup and leakage have been investigated in detail
becauseoftheforwardbiasingofthesubstratesofMOSFETsinCMOS.Theproposed
reference has very low temperature dependence by using a MOSFET with body effect
compared with other reported low-power references. An HSPICE simulation shows
that the reference voltage and the total power dissipation are 181 mV and 1.1 µW,
respectively. The temperature coefficient of the reference voltage is 33 ppm/◦C at
temperatures from -40 to 100 ◦C. The supply voltage can be as low as 0.95 V in a
standard CMOS 0.35 µm technology with threshold voltages of about 0.5 V and -
0.65 V for n-channel and p-channel MOSFETs, respectively. Furthermore, the supply
∼
voltage dependence is -0.36 mV/V (Vdd=0.95 3.3 V).
In the third chapter, the second key cell circuit, a fast lock charge pump phase-
locked loop (CPPLL) without extra power dissipation is proposed. The low-power
PLL design technique is also one of the key issues in analog circuit design. To realize
fast lock without extra power dissipation, a continuous-time phase frequency detector
(PFD) based on the conventional tri-state PFD is proposed. The locking time of the
PLL can be substantially reduced with the proposed continuous-time scheme. During
theperiodthatthebesttracingandacquisitionpropertiesarerequired, thebandwidth
of the PLL is expanded to decrease the locking time with the proposed continuous-

time PFD. Afterwards, the bandwidth of the PLL is recovered to the original value to
minimize output jitter due to external noise. Therefore, no extra power is consumed
compared with conventional PLL. Any conventional tri-state PFDs can be improved
withtheproposedcontinuous-time architecture. Theproposedarchitecture isrealized
inastandardCMOS0.35µmtechnology. Thesimulationresultsdemonstratethatthe
proposed continuous-time PFD is effective to get more speedy locking time without
extra power dissipation.
In the fourth chapter, a novel energy management circuit is proposed for self-
poweredubiquitous sensor modulesusing avariableandweak ambient energy. Energy
is requested by any kind of devices to become functional. Hence many concerns are
applied to power management schemes for any system engineers. In this chapter, the
background of ambient energy source and the properties of the selected ambient en-
ergy for ubiquitous sensor modules are reviewed firstly. Then, an energy management
circuit is proposed for self-powered ubiquitous sensor modules using vibration-based
energy. With the proposed circuit, the sensor modules work with low duty cycle op-
eration. Moreover, a two-tank circuit as a part of the energy management circuit is
proposed to solve the problem that the average power density of ambient energy al-
ways varies with time while the power consumption of the sensor modules is constant
and larger than it. In addition, the long start-up time problem is also avoided with
the timing control of the proposed energy management circuit. The CMOS imple-
mentation and silicon verification results of the proposed circuit are also presented.
Its validity is further confirmed with a vibration-based energy generation. The sensor
moduleisusedtosupervise thevibrationofmachines andtransfer thevibrationsignal
discontinuously. A piezoelectric element acts as the vibration-to-electricity converter
to realize battery-free operation.
In the fifth chapter, a high efficiency charge pump power management circuit

is proposed. Charge pump circuits are frequently used in semiconductor integrated
circuits to provide a voltage that is higher than the voltage of a power supply. If
the output voltage of energy source for low-powered ubiquitous device is small, then
the high efficiency charge pump circuit is one of good solutions to convert a small
or weak input voltage to a higher stable DC voltage as power supply voltage for
ubiquitous device. In addition, the proposed circuit is particularly useful in flash and
EEPROM non-volatile memories because that programming or erasing the memory
cells needs very high positive and negative voltages. Besides, the charge pump circuit
has become an important circuit technique in low-supply-voltage system in order
to increase dynamic range and simplify circuit design. The proposed circuit can
reduce the equivalent on-resistance of the charge-transfer transistors and can avoid
the body effect due to the two pumping branches architecture. Therefore, its voltage
pumping efficiency is much higher than that of the conventional designs. Moreover,
the maximum gate-source, gate-drain and drain-source voltages of all transistors in
the proposed charge pump circuit do not exceed the power supply voltage Vdd. The
proposed charge pump circuit has been realized in a standard CMOS N-Well 0.35
µm technology. The measured results demonstrate that the proposed charge pump
circuit has very high voltage pumping efficiency without overstress and the proposed
charge pump circuit can be realized in any low-voltage single-well standard CMOS
technologies.
In the sixth chapter, the conclusions and the scope for future works are presented.
Keywords: CMOS, Low-Voltage, Low-Power, Ubiquitous, Voltage Reference,
BodyEffect, PLL, FastLock, PFD, Continuous-Time, FrequencyJump, WSN, Battery-
Free, Ambient Energy, Power Management, Self-Powered, Vibration-Based Energy,
Two-Tank, Sensor Modules, Piezoelectric Element, Charge Pump, Overstress, High
Efficiency, Level Shifter.