CLC030 292M/259M Dig Vid Serial w/ Vid & Ancillary Data FIFOs & Int Cable Drvr

34 Pages·2013·0.36 MB·English

OBSOLETE
CLC030
www.ti.com SNLS135F–DECEMBER2000–REVISEDAPRIL2013
CLC030 SMPTE 292M/259M Digital Video Serializer with Video and Ancillary Data FIFOs
and Integrated Cable Driver
CheckforSamples:CLC030
FEATURES APPLICATIONS
1
• SDTV/HDTVSerialDigitalVideoStandard • SDTV/HDTVParallel-To-SerialDigital Video
2
Compliant Interfacesfor:
• Supports270Mbps,360Mbps,540Mbps, – VideoCameras
1.4835Gbpsand 1.485GbpsSDV DataRates – VTRs
withAuto-Detection
– Telecines
• LSBDitheringOption
– Digital VideoRouters andSwitchers
• NoExternalSerialDataRateSettingorVCO
– Digital VideoProcessingandEditing
FilteringComponentsRequired*
Equipment
• FastPLLLockTime:< 150µsTypicalat1.485
– VideoTestPatternGeneratorsandDigital
Gbps
VideoTestEquipment
• AdjustableDepthVideoFIFOforTiming
– VideoSignalGenerators
Alignment
• Built-InSelf-Test(BIST)andVideoTestPattern DESCRIPTION
Generator(TPG)*
The CLC030 SMPTE 292M/259M Digital Video
• AutomaticEDH/CRCWordand Flag Serializer with Ancillary Data FIFO and Integrated
GenerationandInsertion Cable Driver is a monolithic integrated circuit that
encodes, serializes and transmits bit-parallel digital
• On-ChipAncillaryDataFIFOandInsertion
video data conforming to SMPTE 125M and 267M
ControlCircuitry
standard definition, 10-bit wide component video and
• FlexibleControl and ConfigurationI/OPort SMPTE260M, 274M, 295Mand296Mhigh-definition,
• LVCMOSCompatibleDataand ControlInputs 20-bit wide component video standards. The CLC030
andOutputs operates at SMPTE 259M serial data rates of 270
Mbps, 360 Mbps, the SMPTE 344M serial data rate
• 75Ω ECL-Compatible, Differential,Serial Cable-
of 540 Mbps; and the SMPTE 292M serial data rates
DriverOutputs
of 1.4835 and 1.485 Gbps. The serial data clock
• 3.3VI/OPowerSupply,2.5VLogicPower frequency is internally generated and requires no
SupplyOperation external frequency setting, trimming or filtering
• LowPower: Typically430mW components.
• 64-pinTQFPPackage
• CommercialTemperatureRange0°Cto+70°C
*PatentApplicationsMadeor Pending.
1
Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsof
TexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet.
Alltrademarksarethepropertyoftheirrespectiveowners.
2
PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©2000–2013,TexasInstrumentsIncorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarilyincludetestingofallparameters.
OBSOLETE
CLC030
SNLS135F–DECEMBER2000–REVISEDAPRIL2013 www.ti.com
DESCRIPTION (CONTINUED)
The CLC030 performs functions which include: parallel-to-serial data conversion, SMPTE standard data
encoding, NRZ to NRZI data format conversion, serial data clock generation and encoding with the serial data,
automatic video rate and format detection, ancillary data packet management and insertion, and serial data
output driving. The CLC030 has circuitry for automatic EDH/CRC character and flag generation and insertion per
SMPTE RP-165 (standard definition) or SMPTE 292M (high definition). Optional LSB dithering is implemented
which prevents pathological pattern generation. Unique to the CLC030 are its video and ancillary data FIFOs.
The video FIFO allows the video data to be delayed from 0 to 4 parallel data clock periods for video timing
purposes. The ancillary data port and on-chip FIFO and control circuitry store and insert ancillary flags, data
packets and checksums into the ancillary data space. The CLC030 also has an exclusive built-in self-test (BIST)
andvideotestpatterngenerator(TPG)withSDandHDcomponent videotest patterns:referenceblack,PLLand
EQ pathologicals and color bars in 4:3 and 16:9 raster formats for NTSC and PAL standards*. The color bar
patternsfeatureoptionalbandwidthlimitingcodinginthechromaandlumatransitions.
The CLC030 has a unique multi-function I/O port for immediate access to control and configuration settings. This
port may be programmed to provide external access to control functions and indicators as inputs and outputs.
The designer can thus customize the CLC030 to fit the desired application. At power-up or after a reset
command, the CLC030 is auto-configured to a default operating condition. Separate power pins for the output
driver,PLLandtheserializerimprovepowersupplyrejection,output jitterandnoiseperformance.
The CLC030's internal circuitry is powered from +2.5V and the I/O circuitry from a +3.3V supply. Power
dissipation is typically 430mW at 1.485Gbps including two 75Ω AC-coupled and back-matched output loads. The
deviceispackagedina64-pinTQFP.
Typical Application
V
DD
75: SMPTE 292M
SMPTE Video 1% or 259M
Data Input
Serial Data
CLC030VEC
SD/HD Encoder/ Serializer/
Cable Driver
Parallel Ancilliary 1PF
Data Input
75: Coaxial Cable
1PF
Adaptive Cable
Equalizer
75:
1%
SMPTE Video
Data Output
CLC031VEC
SD/HD Decoder/
Deserializer
Parallel Ancilliary
Data Output
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Block Diagram
RESET
RESET
INT.
BUILT-IN SELF-TEST CONTROL
RESET
& TEST PATTERN GENERATOR
P
P CLK
CLK
TRS &
FORMAT
DETECTOR
DV[19:10]
VIDEO
INPUT DATA P
DATA CLK
LATCH
DV[9:0] FIFO
V
CLK
S
U
B
ANC /CTRL R
E
T
ANCILLIARY S
A
DATA FIFO M EDH / CRC
AD[9:0] GENERATORS
P
CLK
A
CLK
CONFIGURATION
RD/WR
& CONTROL DITHERING
P
CLK
REGISTERS
P SMPTE SCRAMBLER
CLK
NRZI CONVERTER
I/O[7:0] MULTI-FUNCTION I/O PORT SCLK SERIALIZER
R LVL
REF
SDO
SYSTEM
VCLK PLL SYSTEM PCLK MASTER SDO
S CONTROLLER
CLK
R PRE
REF
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Connection Diagram
D D
D D PLL PLL
VDD DV9 DV8 DV7 DV6 DV5 VSS DV4 DV3 DV2 DV1 DV0 O1 O0 VSS VDD
I I
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
V 17 64 RESET
SSD
DV10 18 63 VCLK
DV11 19 62 V
DDPLLA
DV12 20 61 V
SSPLLA
DV13 21 60 V
DDZ
DV14 22 59 V
SSLS
V 23 58 SDO
DDIO
DV15 24 57 V
CLC030VEC DDLS
DV16 25 56 SDO
DV17 26 55 V
SSSD
DV18 27 54 V
SSSD
DV19 28 53 R LVL
REF
V 29 52 R PRE
SSIO REF
IO2 30 51 V
DDSD
IO3 31 50 ANC/CTRL
IO4 32 49 RD/WR
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
IO5 IO6 IO7 CLK VDDD AD0 AD1 AD2 AD3 AD4 VSSD AD5 AD6 AD7 AD8 AD9
A
Figure1. 64-PinTQFP
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Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam
duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates.
Absolute Maximum Ratings(1)(2)
CMOSI/OSupplyVoltage
(V –V ): 4.0V
DDIO SSIO
SDOSupplyVoltage
(V –V ): 4.0V
DDSD SSSD
DigitalLogicSupplyVoltage
(V –V ): 3.0V
DDD SSD
PLLDigitalSupplyVoltage
(V –V ): 3.0V
DDPLL SSPLL
PLLAnalogSupplyVoltage
(V –V ),(V −V ): 3.0V
DDPLLA SSPLLA DDZ SSD
CMOSInputVoltage V −0.15VtoV
SSIO DDIO
(Vi): +0.15V
CMOSOutputVoltage V −0.15VtoV
SSIO DDIO
(Vo): +0.15V
CMOSInputCurrent(singleinput): Vi=V −0.15V: −5mA
SSIO
Vi=V +0.15V: +5mA
DDIO
CMOSOutputSource/SinkCurrent: ±10mA
SDOOutputSinkCurrent: 40mA
PackageThermalResistance θ @0LFMAirflow 47°C/W
JA
θ @500LFMAirflow 27°C/W
JA
θ 6.5°C/W
JC
StorageTemp.Range: −65°Cto+150°C
JunctionTemperature: +150°C
LeadTemperature(Soldering4Sec): +260°C
ESDRating(HBM): 2kV
ESDRating(MM): 250V
(1) “AbsoluteMaximumRatings”arethoseparametervaluesbeyondwhichthelifeandoperationofthedevicecannotbeensured.The
statinghereinofthesemaximumsshallnotbeconstruedtoimplythatthedevicecanorshouldbeoperatedatorbeyondthesevalues.
Thetableof“ElectricalCharacteristics”specifiesacceptabledeviceoperatingconditions.
(2) IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheTexasInstrumentsSalesOffice/Distributorsforavailabilityand
specifications.
Recommended Operating Conditions
Symbol Parameter Conditions Reference Min Typ(1) Max Units
V CMOSI/OSupplyVoltage V −V 3.150 3.300 3.450 V
DDIO DDIO SSIO
V SDOSupplyVoltage V −V 3.150 3.300 3.450 V
DDSD DDSD SSSD
V DigitalLogicSupplyVoltage V –V 2.375 2.500 2.625 V
DDD DDD SSD
V PLLSupplyVoltage V –V 2.375 2.500 2.625 V
DDPLL DDPLL SSPLL
V AnalogSupplyVoltage V –V 2.375 2.500 2.625 V
DDZ DDZ SSD
V CMOSInputVoltage,Low
IL V V
Level SSIO
V CMOSInputVoltageHigh
IH V V
Level DDIO
T OperatingFreeAir
A 0 +70 °C
Temperature
t VideoClockJitter V 30 ps
JIT CLK P-P
(1) Averagevaluemeasuredbetweenrisingedgescomputedoveratleastonevideofield.
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DC Electrical Characteristics
OverSupplyVoltageandOperatingTemperatureranges,unlessotherwisespecified(1)(2).
Symbol Parameter Conditions Reference Min Typ(3) Max Units
V InputVoltageHighLevel AllLVCMOS 2.0 V V
IH DDIO
Inputs
V InputVoltageLowLevel V 0.8 V
IL SSIO
I InputCurrentHighLevel V =V +90 +150 µA
IH IH DDIO
I InputCurrentLowLevel V =V −1 −20 µA
IL IL SSIO
V CMOSOutputVoltageHigh I =−6.6mA AllLVCMOS
OH OH 2.4 2.7 V V
Level Outputs DDIO
V CMOSOutputVoltageLow I =+6.6mA V V
OL OL V SSIO SSIO V
Level SSIO +0.3 +0.5V
V SerialDriverOutputVoltage TestCircuit,TestLoads SDO,SDO
SDO 720 800 880 mV
ShallApply P-P
I (3.3V) PowerSupplyCurrent,3.3V V =27MHz,NTSCcolor V ,V
DD CLK DDIO DDSD
Supply,Total BarPattern,TestCircuit, 48 65 mA
TestLoadsShallApply
I (3.3V) PowerSupplyCurrent,3.3V V =74.25MHz,NTSC V ,V
DD CLK DDIO DDSD
Supply,Total colorBarPattern,Test
66 90 mA
Circuit,TestLoadsShall
Apply
I (2.5V) PowerSupplyCurrent,2.5V V =27MHz,NTSCcolor V ,V ,
DD CLK DDD DDZ
Supply,Total BarPattern,TestCircuit, V 66 85 mA
DDPLL
TestLoadsShallApply
I (2.5V) PowerSupplyCurrent,2.5V V =74.25MHz,NTSC V ,V ,
DD CLK DDD DDZ
Supply,Total colorBarPattern,Test V
DDPLL 85 110 mA
Circuit,TestLoadsShall
Apply
(1) Currentflowintodevicepinsisdefinedaspositive.Currentflowoutofdevicepinsisdefinedasnegative.Allvoltagesarereferencedto
V =0V.
SS
(2) TypicalvaluesarestatedforV =V =+3.3V,V =V =+2.5VandT =+25°C.
DDIO DDSD DDD DDPLL A
(3) Averagevaluemeasuredbetweenrisingedgescomputedoveratleastonevideofield.
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AC Electrical Characteristics
OverSupplyVoltageandOperatingTemperatureranges,unlessotherwisespecified(1).
Symbol Parameter Conditions Reference Min Typ(2) Max Units
f ParallelVideoClock V
VCLK CLK 27 74.25 MHz
Frequency
DC VideoClockDutyCycle V 45 50 55 %
V CLK
f AncillaryClockFrequency A V MHz
ACLK CLK CLK
DC AncillaryClockDuty A
A CLK 45 50 55 %
Cycle
t,t InputClockandDataRise 10%–90% V ,A ,DV ,
r f CLK CLK N 1.0 1.5 3.0 ns
Time,FallTime AD
N
BR SerialDataRate See(3)(4) SDO,SDO 270 1,485 M
SDO bps
t,t RiseTime,FallTime 20%–80%(4) SDO,SDO 270 ps
r f
t,t RiseTime,FallTime 20%–80%(3) SDO,SDO 500 ps
r f
OutputOvershoot See(5) SDO,SDO 5 %
t SerialOutputJitter, 270M (3)(6)(7) SDO,SDO
j bps 200 ps
Intrinsic P-P
t SerialOutputJitter, 1,485M (4)(6)(7) SDO,SDO
j bps 120 ps
Intrinsic P-P
t LockTime (SDRates)(3)(8) 15 ms
LOCK
t LockTime (HDRates)(4)(8) 15 ms
LOCK
t SetupTime,VideoData TimingDiagram(5) DV toV 1.5 2.0 ns
S N CLK
t HoldTime,VideoData TimingDiagram(5) V toDV 1.5 2.0 ns
H CLK N
t SetupTime,Anc.Data TimingDiagram(5) AD toA
S N CLK 1.5 2.0 ns
Port
t HoldTime,Anc.DataPort TimingDiagram(5) A toAD 1.5 2.0 ns
H CLK N
(1) TypicalvaluesarestatedforV =V =+3.3V,V =V =+2.5VandT =+25°C.
DDIO DDSD DDD DDPLL A
(2) Averagevaluemeasuredbetweenrisingedgescomputedoveratleastonevideofield.
(3) R =75Ω,AC-coupled@270M ,R LVL=R PRE=4.75kΩ1%,SeeTestLoadsandTestCircuit.
L bps REF REF
(4) R =75Ω,AC-coupled@1,485M ,R LVL=R PRE=4.75kΩ1%,SeeTestLoadsandTestCircuit.
L bps REF REF
(5) Spec.isensuredbydesign.
(6) IntrinsictimingjitterismeasuredinaccordancewithSMPTERP184-1996,SMPTERP192-1996andtheapplicableserialdata
transmissionstandard,SMPTE259M-1997orSMPTE292M(proposed).Acolorbartestpatternisused.Thevalueoff is270MHz
SCLK
or360MHzforSMPTE259M,540MHzforSMPTE344Mor1,485MHzforSMPTE292Mserialdatarates.SeeTimingJitterBandpass
section.
(7) IntrinsicjitterisdefinedinaccordancewithSMPTERP184-1996as:jitteratanequipmentoutputintheabsenceofinputjitter.As
appliedtothisdevice,theinputportisV andtheoutputportisSDOorSDO.
CLK
(8) Measuredfromrising-edgeoffirstDV cycleuntilLockDetectoutputgoeshigh(true).Locktimeincludesformatdetectiontimeplus
CLK
PLLlocktime.
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Test Loads
V
DDSD
V
DDIO
I 75: 75: test eqpt.
OL
1% (attenuation
Hi-Z test eqpt. t 5k: 0dB)
S
1 (attenuation 0dB) SDO
CMOS SDO
outputs
C 1.0PF
L
C I
L OH
S
2
V
DDSD
50: test eqpt.
5.5-30pF*
C including probe and jig 75: (attenuation
L
capacitance, 3pF max. 1% 3.5dB)
S - open, S - closed for V
1 2 OH
measurement SDO
S - closed, S - open for V SDO
1 2 OL 24.9:
measurement
1.0PF 1%
C * risetime
L
compensation
Timing Jitter Bandpass
0dB
slopes: Passband ripple
20dB/decade < ±1dB
s
s
a
p
d
n
a
B
r
e
t
t
Ji
Stopband rejection
>20dB
10Hz Jitter Frequency >1/10 f
SCLK
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Test Circuit
+3.3
Vdc
4.7uF 0.1uF
+2.5 16V (x4)
Vdc 16,
37 1 62 60 51 57 23
(x4)
D D A Z D S O
63 VCLK VDD VDDPLL VDDPLL VDD VDDS VDDL VDDI IO0 3
5 2.5V 3.3V 4
DV0 IO1
Supply Supply
6 30
DV1 IO2 4.7uF 0.1uF
7 31 16V (x3)
DV2 IO3 (x3)
8 32
DV3 IO4
9 33
DV4 HD Chroma, IO5
SD Luma & Chroma
11 34
DV5 IO6
12 35
DV6 IO7
13 36
DV7 ACLK
14 38
DV8 AD0 Output loads omitted for
15 39 clarity.
DV9 AD1
18 40
DV10 AD2
CLC030VEC
19 41
DV11 AD3
20 42
DV12 AD4
21 44
DV13 AD5
22 45
DV14 AD6
24 HD Luma 46 +3.3 V
DV15 AD7
25 47 75:1%
DV16 AD8
26 48
DV17 AD9 1.0uF
27 56
DV18 SDO
28 58
DV19 SDO
50 53
ANC/CTRL R LVL
REF
49 52
RD/WR R PRE
REF
64 +3.3 V
RESET 2.5V 3.3V
Supply Supply 75:(cid:3)1%
D A
SD SPLL SPLL SSD SIO SLS
S S S S S S 1.0uF
V V V V V V
10, 2 61 54, 29 59
0 Vdc 17, 43 55 4.75k 4.75k
1% 1%
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Timing Diagram
90% 90%
VCLK
(ACLK) 50% tr, tf
10% 10%
t
H
t
S
90%
DV[19:0]
(AD[9:0]) tr, tf
10%
Device Operation
The CLC030 SDTV/HDTV Serializer is used in digital video signal origination equipment: cameras, video tape
recorders, telecines and video test and other equipment. It converts parallel SDTV or HDTV component digital
video signals into serial format. Logic levels within this equipment are normally produced by LVCMOS logic
devices. The encoder produces serial digital video (SDV) signals conforming to SMPTE 259M, SMPTE 344M
(proposed) or SMPTE 292M. The CLC030 operates at parallel data rates of 27.0 MHz, 36.0 MHz, 54.0 MHz,
74.176MHz and 74.25 MHz. Corresponding serial data rates are 270 Mbps, 360 Mbps, 540 Mbps, 1.4835Gbps
and1.485Gbps.
VIDEO DATA PATH
The input data register accepts 10-bit standard definition or 20-bit high definition parallel data and associated
parallel clock signals having LVCMOS-compatible levels. All parallel video data inputs, DV[19:0], have internal
pull-down devices. VCLK does not have an internal pull-down device. Parallel video data may conform to any of
several SMPTE standards: 125M, 267M, 260M, 274M, 295M or 296M. Some segmented frame formats are not
supported. For HDTV data, the upper 10 bits of the DV input are luminance (luma) information and the lower 10
bits are color difference (chrominance or chroma) information. For SDTV data, the lower order 10 bits contain
both luma and chroma information. Output from this register feeds the video FIFO, video format detection circuit,
TRS character detector, SMPTE scrambler, EDH/CRC generators, serializer/NRZI converter and the device
controlsystem.
Data from the input data register passes into a 4-register deep video FIFO prior to encoding and other
processing.ThedepthofthisFIFOissetbytheVIDEO FIFODepth[2:0]bitsoftheANC0controlregister.
The video format detector automatically determines the raster characteristics (video data format) of the parallel
input data and configures the CLC030 to properly handle the data. This assures that the data will be properly
formatted, that the correct data rate is selected and that ancillary data, line numbers (HD) and CRC/EDH data
are correctly inserted. Indication of the standard being processed is stored in the FORMAT[4:0] bits in the
FORMAT 1controldataregister.Thisformatdatacanbeprogrammedfor output onthemulti-functionI/Oport.
TheCLC030normallyoperatesinanauto-format-detectionmode. It mayoptionallybeconfiguredtoprocessonly
a single video format by writing the appropriate FORMAT SET[4:0] control data into the FORMAT 0 control
register. The default state of FORMAT SET[4:0] is 0000b. Also, the CLC030 may be configured to handle only
thestandard-definitiondataformatsbysettingtheSDONLYbit or only the high-definition data formats by setting
the HD ONLY bit in the FORMAT 0 control register. When both of these bits are reset the part automatically
selectsthedatarate.
The TRS character detector processes the timing reference signals which control raster framing. The TRS
detector supplies control signals to the system controller to identify the presence of the valid video data. The
system controller supplies necessary control signals to the EDH/CRC control block. TRS character LSB-clipping
as prescribed in ITU-R BT.601 is used. LSB-clipping causes all TRS characters with a value between 000h and
003h to be forced to 000h and all TRS characters with a value between 3FCh and 3FFh to be forced to 3FFh.
ClippingisdonepriortoscramblingandEDH/CRCcharactergeneration.
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