CLASS D AUDIO AMPLIFIER A Major Qualifying Project Report

344 Pages·2008·36.61 MB·English

CLASS D AUDIO AMPLIFIER

A Major Qualifying Project Report:

submitted to the Faculty

of the

WORCESTER POLYTECHNIC INSTITUTE

in partial fulfillment of the requirements for the

Degree of Bachelor of Science

by

______________________

Justin Cox

______________________

John Durst

______________________

Jayce Silvia

Date: April 20, 2008

Approved:

_____________________________

Professor Stephen J. Bitar, Advisor
Abstract
This project consisted of the design, construction, and comparison testing of two
implementations of analog pulse-width modulation Class D audio amplifiers. The main goal of the
project was to maximize the efficiency of the amplifier designs while maintaining a high-power, low-
noise output signal. PCB testing confirmed that the amplifiers met our goals of greater than 90%
efficiency, less than 1% total harmonic distortion and greater than 50 W output power.

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Table of Contents

Abstract ......................................................................................................................................................... ii
Table of Figures ............................................................................................................................................ vi
Table of Tables ............................................................................................................................................. ix
Table of Equations ........................................................................................................................................ x
1. Background ............................................................................................................................................... 1
1.1. What is Class D? ................................................................................................................................. 1
1.1.1. Other Classes .............................................................................................................................. 2
1.1.2. Common applications................................................................................................................. 4
1.1.3. Market Share .............................................................................................................................. 5
1.2. Design Considerations........................................................................................................................ 5
1.2.1. Half Bridge vs. Full Bridge ........................................................................................................... 5
1.2.2. Two-level vs. Three-level PWM .................................................................................................. 8
1.3. MOSFETs vs. BJTs ............................................................................................................................... 8
1.3.1. MOSFET Selection parameters ................................................................................................. 10
1.4. Battery Selection .............................................................................................................................. 11
1.5. Modulation Techniques ................................................................................................................... 12
1.5.1. Pulse-width Modulation ........................................................................................................... 12
1.5.2. Pulse-density Modulation ........................................................................................................ 13
1.6. EMI Reduction Techniques .............................................................................................................. 13
1.6.1. EMI Testing Standards .............................................................................................................. 15
1.6.2. Spread-Spectrum Modulation (SSM) ....................................................................................... 16
1.6.3. Other techniques for EMI reduction ........................................................................................ 17
1.6.3.1. Filtering ................................................................................................................................. 18
1.6.3.2. Ferrite Beads ......................................................................................................................... 19
1.6.3.3. Active Emissions Limiting (AEL) ............................................................................................. 20
1.6.4. PCB Layout Optimization .......................................................................................................... 22
1.7. Special Features ............................................................................................................................... 24
1.8. Power Losses and System Efficiency ................................................................................................ 25
1.8.1. Power Output ........................................................................................................................... 25
1.9. Ideal Circuit Simulations .................................................................................................................. 26
2. Project Definition .................................................................................................................................... 28
3. Project Design ......................................................................................................................................... 29
3.1. PWM Switching ................................................................................................................................ 29
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3.1.1. Switching Logic and Basic Concepts ......................................................................................... 29
3.1.2. Offset Voltage........................................................................................................................... 30
3.2. Filter Design ..................................................................................................................................... 31
3.2.1. Introduction & Theory .............................................................................................................. 31
3.2.2. Design Process .......................................................................................................................... 32
3.2.3. Alternative Structures .............................................................................................................. 33
3.2.4. Transfer Function ..................................................................................................................... 34
3.2.5. Calculating Values .................................................................................................................... 35
3.2.6. Software Simulation ................................................................................................................. 36
3.2.7. Part Selection ........................................................................................................................... 38
3.2.8. Real-World Testing ................................................................................................................... 39
3.3. Triangle Wave Generation ............................................................................................................... 39
3.3.1. Op-amp Configuration .............................................................................................................. 40
3.3.2. Desired Specifications .............................................................................................................. 41
3.3.3. Simulation Results .................................................................................................................... 42
3.3.4. Part Selection ........................................................................................................................... 44
3.3.5. Testing ...................................................................................................................................... 45
3.4. Spread Spectrum Design .................................................................................................................. 47
3.5. Feedback and System Stability ......................................................................................................... 47
3.6. Power Stage ..................................................................................................................................... 51
3.6.1. Power Supply ............................................................................................................................ 51
3.6.2. Power Losses ............................................................................................................................ 52
3.6.3. Control Logic............................................................................................................................. 55
3.6.4. Part Selection ........................................................................................................................... 56
4. Project Schedules .................................................................................................................................... 57
4.1. Proposed Schedule for B Term 2007 ............................................................................................... 57
4.2. Proposed Schedule for C Term 2008 ............................................................................................... 58
5. Project Evolution and Design Changes ................................................................................................... 59
5.1. Two-Level PWM Board..................................................................................................................... 59
5.1.1. Final Part Selection ................................................................................................................... 59
5.1.2. Breadboard Prototype and Issues ............................................................................................ 59
5.1.3. First PCB ................................................................................................................................... 64
5.2. Three-Level PWM Board .................................................................................................................. 79
5.2.1. Final Component Selection ...................................................................................................... 80
5.2.2. Breadboard Prototype and Issues ............................................................................................ 82
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5.2.3. First PCB ................................................................................................................................... 84
6. Performance Testing and Characterization ............................................................................................ 97
6.1. System Gain ..................................................................................................................................... 97
6.1.1. Two-Level Board ....................................................................................................................... 99
6.1.2. Three-Level Board .................................................................................................................. 101
6.2. Output Power ................................................................................................................................. 103
6.2.1. Calculations and Measurement Methodology ....................................................................... 103
6.2.2. Two Level Power Testing ........................................................................................................ 105
6.2.3. Three Level Power Testing ..................................................................................................... 106
6.3. Efficiency ........................................................................................................................................ 109
6.4. Total Harmonic Distortion ............................................................................................................. 112
6.4.1. Two-Level Board ..................................................................................................................... 112
6.4.2. Three-Level Board .................................................................................................................. 114
6.5. Summary of Testing Results ........................................................................................................... 116
6.5.1. Two-Level Board ..................................................................................................................... 117
6.5.2. Three-Level Board .................................................................................................................. 117
6.6. Qualitative Testing ......................................................................................................................... 118
7. Recommendations ................................................................................................................................ 119
8. Conclusions ........................................................................................................................................... 121
A. References ........................................................................................................................................ 122
B. MOSFET Data Sheets ........................................................................................................................ 125
C. Battery Selection Data Sheets .......................................................................................................... 126
D. Maxim Description of Figure 1.17 .................................................................................................... 127
E. THD Testing Data .............................................................................................................................. 128
F. Project Expenses .............................................................................................................................. 149
G. Part Datasheets ................................................................................................................................ 150

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Table of Figures
Figure 1.1 Class D Diagram............................................................................................................................ 1
Figure 1.2 Class A Diagram ............................................................................................................................ 2
Figure 1.3 Class B Diagram ............................................................................................................................ 3
Figure 1.4 Class B Push-Pull Configuration with Crossover Distortion ......................................................... 3
Figure 1.5 Class AB Diagram.......................................................................................................................... 4
Figure 1.6 Half Bridge With Connected Load Schematic .............................................................................. 6
Figure 1.7 Example BTL configuration .......................................................................................................... 7
Figure 1.8 Typical Pulse-width Modulation Signal ...................................................................................... 13
Figure 1.9 Pulse-density Modulation .......................................................................................................... 13
Figure 1.10 Square Wave Parameters ........................................................................................................ 15
Figure 1.11 FCC Radiated Emissions Standards .......................................................................................... 16
Figure 1.12 Spread-spectrum Modulation Theory ...................................................................................... 17
Figure 1.13 Second Order Balanced Filter .................................................................................................. 18
Figure 1.14 Half Filter .................................................................................................................................. 19
Figure 1.15 Ferrite Bead Frequency Response ........................................................................................... 20
Figure 1.16 Maxim AEL Performance .......................................................................................................... 21
Figure 1.17 Maxim Filterless Design With AEL ............................................................................................ 22
Figure 1.18 LM4673 and LM4674 ............................................................................................................... 24
Figure 1.19 Ideal Model .............................................................................................................................. 26
Figure 1.20 Ideal Waveforms ...................................................................................................................... 27
Figure 3.1 Schematic for PWM Switching Scheme ..................................................................................... 29
Figure 3.2 Typical LC Output Filter (Shown With Power Stage) .................................................................. 32
Figure 3.3 Example Speaker Impedance vs. Frequency .............................................................................. 33
Figure 3.4 Balanced Filter Design ................................................................................................................ 33
Figure 3.5 Low Pass Filter For Full Bridge ................................................................................................... 34
Figure 3.6 Divided Low Pass Filter For Full Bridge ...................................................................................... 34
Figure 3.7 Filter Simulation Circuit .............................................................................................................. 36
Figure 3.8 Filter Magnitude Response vs. Frequency ................................................................................. 37
Figure 3.9 Balanced Filter Simulation Circuit .............................................................................................. 37
Figure 3.10 Balanced Filter Frequency Response ....................................................................................... 38
Figure 3.11 Triangle Wave Generator Design ............................................................................................. 40
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Figure 3.12 Triangle Wave Generator Simulation Circuit ........................................................................... 42
Figure 3.13 Triangle Wave Generator Simulation Waveforms – First Design ............................................ 43
Figure 3.14 Triangle Waveform Simulation Waveforms – Second Design ................................................. 44
Figure 3.15 Triangle Wave Generator Schematic ....................................................................................... 46
Figure 3.16 Oscilloscope Display Showing Triangle Wave Generator ........................................................ 46
Figure 3.17 Final Triangle Wave Generator ................................................................................................ 47
Figure 3.18 Simple Feedback System .......................................................................................................... 48
Figure 3.19 Feedback System For Half-Bridge ............................................................................................ 49
Figure 3.20 Feedback System For Full Bridge ............................................................................................. 49
Figure 3.21 Circuit Diagram Of The Power Stage ........................................................................................ 51
Figure 3.22 MOSFET Switching Scheme ...................................................................................................... 53
Figure 3.23 Current Paths for Two-Level Amplifier .................................................................................... 54
Figure 5.1 First Triangle Wave .................................................................................................................... 60
Figure 5.2 Final Two-level Schematic .......................................................................................................... 61
Figure 5.3: Two-level Modulator On Breadboard ....................................................................................... 62
Figure 5.4 Power Stage Attached to Modulator ......................................................................................... 63
Figure 5.5 Two-level Ultiboard Layout (Top) .............................................................................................. 65
Figure 5.6 Two-level Ultiboard Layout (Power Plane) ................................................................................ 66
Figure 5.7 Two-level Ultiboard Layout (Ground Plane) .............................................................................. 66
Figure 5.8 Two-level Ultiboard Layout (Bottom) ........................................................................................ 67
Figure 5.9 Two-level Blank PCB (Top) ......................................................................................................... 68
Figure 5.10 Two-level Blank PCB (Bottom) ................................................................................................. 68
Figure 5.11 Two-level Assembled PCB (Top) .............................................................................................. 70
Figure 5.12 Two-level Triangle Wave Waveform ........................................................................................ 71
Figure 5.13 Two-level Input Waveform ...................................................................................................... 72
Figure 5.14 Two-level Input and Triangle Wave Waveforms ...................................................................... 73
Figure 5.15 Two-level PWM Waveform ...................................................................................................... 74
Figure 5.16 Two-level Schematic with Bypass Capacitors .......................................................................... 75
Figure 5.17 Two-level PCB Assembled with Bypass Capacitors (Bottom) .................................................. 76
Figure 5.18 Two-level Input and Output Waveforms ................................................................................. 77
Figure 5.19 Two-level Input and Differential Output (MATH) Waveforms................................................. 78
Figure 5.20 Final Three Level Schematic With Actual Components ........................................................... 79
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Figure 5.21 Three Level Breadboard ........................................................................................................... 82
Figure 5.22 Three level Triangle Wave (Pre-shifting).................................................................................. 83
Figure 5.23 MOSFET Gate Control Signals. ................................................................................................. 84
Figure 5.24 Three-level Ultiboard Layout (Top) .......................................................................................... 86
Figure 5.25 Three-level Ultiboard Layout (Power Plane) ............................................................................ 86
Figure 5.26 Three-level Ultiboard Layout (Ground Plane) .......................................................................... 87
Figure 5.27 Three-level Ultiboard Layout (Bottom) .................................................................................... 87
Figure 5.28 Three-level Blank PCB (Top) ..................................................................................................... 88
Figure 5.29 Three-level Blank PCB (Bottom) ............................................................................................... 89
Figure 5.30 Three-level PCB Assembled (Top) ............................................................................................ 90
Figure 5.31 Three-level PCB Triangle Wave Waveform .............................................................................. 91
Figure 5.32 Three-level Schematic with Bypass Capacitors ........................................................................ 92
Figure 5.33 Three-level PCB Input and Shifting Triangle Wave Waveforms ............................................... 93
Figure 5.34 Three-level PCB Input and PWM Waveforms .......................................................................... 94
Figure 5.35 Three-level PCB Input and Output Waveforms ....................................................................... 95
Figure 5.36: MOSFET Gate Driving Waveforms .......................................................................................... 95
Figure 5.37 Three-level PWM Input and Differential Output Waveforms .................................................. 96
Figure 6.1 AC Coupling At Input .................................................................................................................. 98
Figure 6.2 Voltage Gain Frequency Response of Two-level PCB .............................................................. 100
Figure 6.3 Voltage Gain Frequency Response of Three-level PCB ............................................................ 102
Figure 6.4 Voltage Gain Frequency Response Comparison ...................................................................... 103
Figure 6.5 Test Load Resistor .................................................................................................................... 105
Figure 6.6 Power Output vs. Frequency Comparison ............................................................................... 107
Figure 6.7 Plot of High Power Voltage Sweep .......................................................................................... 108
Figure 6.8 Efficiency Comparison for Two and Three-level PWM ............................................................ 110
Figure 6.9 Efficiency versus Supply Voltage for 3-Level Amplifier ............................................................ 111
Figure 6.10 Two-level THD vs. Frequency Plot .......................................................................................... 113
Figure 6.11 Three-level THD vs. Frequency Plot ....................................................................................... 115
Figure 6.12 THD vs. Frequency Comparison Plot ...................................................................................... 116

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Table of Tables
Table 1.1 BJT Advantages And Disadvantages ............................................................................................ 10
Table 1.2 MOSFET Advantages And Disadvantages .................................................................................... 10
Table 1.3 Max I vs. Capacitance and Expected R .................................................................................... 11
D DS
Table 1.4 Battery Class And Associated Parameters .................................................................................. 12
Table 3.1 Calculated Values For 20 kHz Cutoff Frequency ......................................................................... 35
Table 3.2 Calculated Values For 30 kHz Filter ............................................................................................. 36
Table 3.3 Part Selection Criterion ............................................................................................................... 38
Table 3.4 Selected Filter Components ........................................................................................................ 39
Table 3.5 Higher Power Filter Parts ............................................................................................................ 39
Table 3.6 Logic Table for MOSFET Switching .............................................................................................. 55
Table 4.1 Proposed Schedule For B Term ................................................................................................... 57
Table 4.2 Proposed Schedule For C Term ................................................................................................... 58
Table 6.1 Two-level Output Amplitude And Gain vs. Frequency Data ....................................................... 99
Table 6.2 Output Amplitude And Gain vs. Frequency for Three-level PCB .............................................. 101
Table 6.3 Summary of Gain Data for Three-level ...................................................................................... 102
Table 6.4 Two-level PWM Power Data ..................................................................................................... 106
Table 6.5 PWM Power Data ...................................................................................................................... 107
Table 6.6 High Voltage Power Outputs ..................................................................................................... 108
Table 6.7 Efficiency Comparison Data ...................................................................................................... 110
Table 6.8 Two-level THD Data ................................................................................................................... 112
Table 6.9 Three-level THD Data ................................................................................................................ 114
Table 6.10 Summary of Testing Results .................................................................................................... 116

ix
Table of Equations
Equation 1.1 Formula For Efficiency of An Amplifier .................................................................................. 25
Equation 3.1 Formula For Power Wasted By On Resistance of MOSFETs .................................................. 52
Equation 3.2 Equation For Switching Loses ................................................................................................ 54
Equation 3.3 Formula For The Efficiency of The Amplifier ......................................................................... 55

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