characterization of mos transistor mismatch for analog design

261 Pages·2014·10.24 MB·English

KATHOLIEKE UNIVERSITEIT LEUVEN
FACULTEIT DER TOEGEPASTE WETENSCHAPPEN
DEPARTEMENT ELEKTROTECHNIEK
Kardinaal Mercierlaan 94, 3001 Leuven (Heverlee)

C
HARACTERIZATION OF
MOS T M
RANSISTOR ISMATCH

FOR
A D
NALOG ESIGN

Promotor: Proefschrift voorgedragen tot het
behalen van het doctoraat in de
Prof. Dr. Ir. W. SANSEN toegepaste wetenschappen
Prof. Dr. Ir. M. STEYAERT
door

Jose Manuel A. T. Bastos

May 1998
A
CKNOWLEDGMENTS
This thesis is the result of the research work that I realized at the ESAT-MICAS group of
the Katholieke Universiteit Leuven. I would like to thank all the people that directly or
indirectly made it possible. In particular, I would like to thank:
• Prof. W. Sansen. Under his leadership, the ESAT-MICAS group became a place of
excellence in Analog Circuit Design. I wish to express my deepest gratitude for having
accepted me in his group, providing me the conditions, both material and social, that
made this work possible. In particular, I am grateful for the freedom of research, for his
ever present cordiality and support, and for the care put in the revisions of this text.
• Prof. M. Steyaert, for having offered me the possibility of cooperating in the Mismatch
Characterization Project, and for his insight and suggestions in crucial moments of the
research.
• Prof. G. Declerck, of the reading committee, Prof. H. De Man, Prof. J. Franca (IST,
Portugal), Ir. E. Laes (Alcatel-Mietec), members of the jury, and Prof. J. Berlamont,
chairman of the jury, for their valuable time spent in the evaluation of this work
• Benny Graindourze and Anelia Pergoot from Alcatel-Mietec, and my colleagues Raf
Roovers and Peter Kinget, for the many fruitful discussions and contributions to this
work on the mismatch characterization.
• My colleague Augusto Marques, for the careful reading of the manuscript, and
especially, for the perfect team-work that made the design of the segmented-architecture
DAC a reality in a record time. On this project, I wish also to acknowledge the fruitful
cooperation with my colleague Jan Vandenbussche and with Anelia Pergoot.
• All my friends at ESAT and in Leuven that have given me a very good social
atmosphere and made my stay here memorable. In particular, I would like to mention a
few: Luis, João, Dorin, Geert, Koenraad, Anca, Enzo, Jan, Ben, Saulo, Igor, Erik,
Francky, Marc, Paulo, and Augusto.
• The people that make the work at the MICAS group to run smoothly: Chris Van
Grieken, Albert Boon, Michel De Cooman, Camille Evers, Piet Vanderwegen, for the
technical support, Wim Eyckmans and Eric Olemans, for the software support, Danielle
Vermetten and Erika Scheltens, for the secretarial support.
• The Portuguese Research Board (JNICT) and the University of Porto (UP), for the
financial support that made my stay at ESAT possible. Prof. M. De Barros and Prof. A.
Leite (UP) for all the support that eventually brought me to ESAT.
• And finally, I thank Quina for her love, and patience with me all these years.
José Bastos
Leuven, April 1998.
v
vi
A
BSTRACT
The performance of many precision analog integrated circuits is limited by the device
matching properties of the technology in which the circuits are fabricated. With the present
trend of integration of digital and analog building blocks in a single-chip design, standard
digital CMOS technologies are often used to design precision analog circuits. However, when
a standard digital CMOS technology is used there are no precision devices available and the
circuit designer can rely only on the matching properties of the MOS transistors. For this
reason, the characterization and modeling of mismatch in MOS transistors has become an
important research topic.
In this work, the characterization of MOS transistor mismatch in two modern
technologies of 1.2 m m and 0.7 m m minimum feature size is presented. All steps of the
mismatch characterization are described in detail: design of a test chip, extraction of
mismatch parameters, validation of the mismatch parameter statistics and of the parameter
statistical models.
It is shown that the standard way of defining mismatch parameters—the difference in the
absolute parameters of two nominally equal transistors—is not appropriate to extract
mismatch parameters of sub-micron transistors. In this work, an alternative method is
proposed: to extract the mismatch parameters by fitting a current mismatch model to the
measured current mismatch curve. It is shown theoretically and experimentally that the
mismatch parameters extracted in this way are more accurate than in the standard way.
Short and narrow channel effects on the matching of the threshold voltage model
parameter are observed: the inverse proportionality law between the variance of the threshold
voltage parameter and the transistor channel area no longer holds for the minimum feature-
size devices. A new threshold voltage parameter statistical model valid for sub-micron
transistors is proposed and experimentally validated in this work.
When attempting to match devices over large distances, systematic errors across the die
become increasingly important. It is shown in this work both theoretically and experimentally
that die gradients due to die-stress originating in the bonding technique are far more
important than those attributed to process steps.
To demonstrate the utility of the characterization of the transistor mismatch for analog
design, a current-steering architecture digital-to-analog converter (DAC) is chosen. The main
characteristic of the architecture, that a large number of transistors must match over relatively
large distances, makes it ideal as a test circuit. The first realized DAC proves the feasibility of
designing with high yield (> 90 %) a 12-bit intrinsic accuracy (no trimming, calibration, or
dynamic averaging) all MOS transistor DAC. The second realized DAC proves that this
accuracy specification can be reached without compromising the dynamic performance of the
DAC. By optimizing all the building blocks, and by using a new architecture, it is shown that
the DAC can work at update rates in excess of 300 MS/s, with state-of-the-art dynamic
specifications.
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C
ONTENTS
ACKNOWLEDGMENTS....................................................................................................v
ABSTRACT .................................................................................................................vii
CONTENTS..................................................................................................................ix
1 Introduction............................................................................................................1
1.1 Historical Perspective....................................................................................................1
1.2 The Impact of Mismatch on Analog Circuit Design......................................................2
1.3 Research Objectives.......................................................................................................3
1.4 Thesis Organization.......................................................................................................4
1.5 Research Contribution...................................................................................................4
PART I CHARACTERIZATION OF MOS TRANSISTOR MISMATCH.........................................7
2 Extraction of Transistor Mismatch Parameters................................................11
2.1 Design of a Test Chip for Mismatch Studies...............................................................12
2.2 Measurement Set-up....................................................................................................16
2.3 Measurement Procedure..............................................................................................17
2.4 Choice of Transistor Models for Mismatch Studies....................................................19
2.4.1 Linear Region.....................................................................................................20
2.4.2 Saturation Region...............................................................................................21
2.4.3 Weak Inversion...................................................................................................22
2.4.4 A General Mismatch Model...............................................................................23
2.5 Extraction of Mismatch Parameters.............................................................................23
2.5.1 Extraction of the D V , Db/b , and Dq Mismatch Parameters in the Linear and
T0
Saturation Regions.......................................................................................................24
2.5.2 Extraction of the Dg Mismatch Parameter..........................................................30
2.5.3 Extraction of the D V Mismatch Parameter in the Weak Inversion Region.....32
T0
2.6 Sensitivity Analysis.....................................................................................................34
2.7 Accuracy of the Mismatch Parameters........................................................................35
2.7.1 Temperature Effect.............................................................................................35
2.7.2 Repeatability Study.............................................................................................36
2.8 Conclusion...................................................................................................................37
3 Current Mismatch Statistical Models.................................................................39
3.1 Mismatch Parameter Statistics.....................................................................................39
3.2 Statistical Results in the Saturation Region.................................................................42
3.2.1 D V , Db/b , and Dq Results...............................................................................42
T0
3.2.2 Dg Results...........................................................................................................44
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X CONTENTS
3.3 Validation of the Extraction Methods..........................................................................44
3.3.2 Model Reduction................................................................................................51
3.4 Towards a general parameter mismatch model...........................................................55
3.4.1 Measurement Results in the Linear Region........................................................55
3.4.2 Measurement Results in Weak Inversion...........................................................58
3.5 Conclusion...................................................................................................................59
4 Random Mismatch...............................................................................................61
4.1 A General Parameter Mismatch Model.......................................................................62
4.2 Mismatch in the Threshold Voltage.............................................................................63
4.2.1 Importance of the Charge Terms........................................................................65
4.2.2 Theoretical Expression for A ...........................................................................66
VT
4.3 Short and Narrow Channel Effects on V ....................................................................67
T
4.3.1 Short-Channel Devices.......................................................................................68
4.3.2 Narrow-Channel devices.....................................................................................69
4.4 Extended Threshold Voltage Mismatch Model...........................................................70
4.5 Threshold Voltage Mismatch Technology Parameters................................................71
4.5.1 C12 Technology..................................................................................................71
4.5.2 C07 Technology..................................................................................................75
4.5.3 Summary.............................................................................................................77
4.6 Mismatch in the Body Effect Factor............................................................................77
4.6.1 Technology Parameters.......................................................................................79
4.6.2 Summary.............................................................................................................83
4.7 Mismatch in the Current Factor...................................................................................84
4.7.2 Technology Parameters.......................................................................................86
4.7.3 Summary.............................................................................................................91
4.8 Limits of Validity of the Mismatch Models................................................................92
4.9 Mismatch Scaling with the Technology......................................................................93
4.9.1 Threshold Voltage...............................................................................................93
4.9.2 Current Factor.....................................................................................................95
4.10 Conclusion.................................................................................................................96
5 Systematic Mismatch..........................................................................................99
5.1 Mismatch due to Wafer Gradients.............................................................................100
5.2 Measurement Results.................................................................................................102
5.2.1 C12 Technology................................................................................................102
5.2.2 C07 Technology................................................................................................105
5.3 Mismatch due to Die Stress.......................................................................................110
5.4 Source-Drain Asymmetry..........................................................................................115
5.5 Mismatch in Large W/L Transistors..........................................................................117
5.5.1 Test Chip with Large W/L Transistor Pairs.......................................................117
5.5.2 Measurement Results........................................................................................119
5.6 A Statistical Mismatch Model...................................................................................123
5.7 Conclusion.................................................................................................................124
Part II A 12-Bit Accuracy D/A Converter.............................................................127
6 Design for High Accuracy and High Yield.......................................................129
6.1 Current Steering Architectures..................................................................................130
CONTENTS xi
6.1.1 Binary Weighted Architecture..........................................................................131
6.1.2 Unit Element Architecture................................................................................134
6.1.3 Segmented Architecture....................................................................................136
6.1.4 Summary...........................................................................................................138
6.2 DAC Accuracy and Yield..........................................................................................138
6.3 Estimation of the Total Current Source Area............................................................140
6.4 Systematic Errors.......................................................................................................141
6.4.1 Graded and Symmetrical Errors........................................................................141
6.4.2 Ground Line Voltage Drop...............................................................................146
6.4.3 Output Impedance.............................................................................................149
6.5 DAC Specifications...................................................................................................150
6.6 Layout Considerations...............................................................................................152
6.6.1 Sizing the Unit Current Source.........................................................................152
6.6.2 Layout of the Current Source Matrix................................................................154
6.6.3 Centroid Layout................................................................................................156
6.7 Non-Linearity Errors..................................................................................................157
6.7.1 Process and Die-Stress Errors...........................................................................158
6.7.2 Voltage Drop in the Ground Line.....................................................................158
6.7.3 Output Resistance Compliance.........................................................................160
6.7.4 Voltage Drop in the Drain Lines.......................................................................161
6.7.5 Temperature Gradient.......................................................................................162
6.8 Random Noise...........................................................................................................163
6.9 Conclusion.................................................................................................................164
7 Design for Speed...............................................................................................165
7.1 DAC Settling Time....................................................................................................165
7.1.1 Optimizing For Maximum Speed And Minimum Area...................................166
7.1.2 Bonding Wire Inductance.................................................................................169
7.1.3 Current Source Output Voltage Fluctuation.....................................................171
7.1.4 Asymmetric and Delayed Control Signals........................................................175
7.1.5 Summary...........................................................................................................181
7.2 DAC glitch energy.....................................................................................................181
7.2.1 Harmonic distortion..........................................................................................181
7.2.2 Asymmetry in the Unit Cell Output Currents...................................................182
7.2.3 Charge Feedthrough..........................................................................................185
7.2.4 Synchronization of the Control Signals............................................................190
7.3 Conclusion.................................................................................................................191
8 Practical Realizations........................................................................................193
8.1 A 12-bit binary weighted DAC..................................................................................193
8.1.1 Layout...............................................................................................................194
8.1.2 Experimental results.........................................................................................196
8.2 A 12-Bit segmented architecture DAC......................................................................202
8.2.1 Decoding Logic.................................................................................................202
8.2.2 DAC Architecture.............................................................................................204
8.2.3 Layout...............................................................................................................208
8.2.4 Experimental Results........................................................................................210
8.3 Conclusion.................................................................................................................214
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XII CONTENTS
9 General Conclusions.........................................................................................217
9.1 Future Research.........................................................................................................219
A TABLES................................................................................................................221
B STATISTICS FOR MATCHING....................................................................................227
C REGRESSION ANALYSIS.........................................................................................231
PUBLICATIONS..........................................................................................................241
BIBLIOGRAPHY.........................................................................................................243
Chapter
I
NTRODUCTION
Precision analog integrated circuit design is based on matched devices: while the absolute
accuracy of the devices on a chip is poor, about 10% or worse, the characteristics of matched
devices can be made to track each other with up to 100 times better relative accuracy
[Laker94, p. 150].
Of several technology alternatives, the preferred technology for precision analog design
has been bipolar. Indeed, it is in bipolar technologies that the best matched devices are
obtained, irrespective of being resistors, capacitors or transistors. However, nowadays the
drive towards digital signal processing has made CMOS by far the most popular of all
integrated circuit technologies, because of the higher device density, the lower power
consumption, and the lower cost when compared with, for example, bipolar, BiCMOS and
GaAs technologies.
The evolution in the CMOS technologies is totally driven by the requirements of digital
circuits: in a standard CMOS technology, precision passive devices (i.e., resistors and
capacitors) are not available. In a mixed analog-digital circuit design in a standard CMOS
technology, the design of the analog part of the circuit is typically made with only two
precision devices: NMOS and PMOS transistors.
1.1 Historical Perspective
The first matching studies of MOS technologies presented in the open literature were
done on capacitors [McCreary81, Shyu82]. It was then established that the causes of random
device mismatch are characterized by mismatch sources with short correlation distances
(compared with the device dimensions). Mismatch sources identified at the time were random
edge variations, and random fluctuations of the thickness and permittivity of the oxide
insulator.
Shyu et al. [Shyu84] extended the previous work to the matching study of current sources.
Random mismatch sources are now qualified in two categories: local (with short correlation
distances), and global (with long correlation distances). Mismatch sources influencing the
1