Chapter 5 - Akira

16 Pages·2013·1.25 MB·English

Chapter 5 Objectives
•  Understand the factors involved in instruction
set architecture design.
•  Gain familiarity with memory addressing
Chapter 5
modes.
A Closer Look at •  Understand the concepts of instruction-level
Instruction Set pipelining and its affect upon execution
performance.
Architectures
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5.1 Introduction 5.2 Instruction Formats
•  This chapter builds upon the ideas in Chapter 4. Instruction sets are differentiated by the following:
•  We present a detailed look at different •  Number of bits per instruction.
instruction formats, operand types, and memory •  Stack-based or register-based.
access methods.
•  Number of explicit operands per instruction.
•  We will see the interrelation between machine
•  Operand location.
organization and instruction formats.
•  Types of operations.
•  This leads to a deeper understanding of
•  Type and size of operands.
computer architecture in general.
Employers frequently prefer to hire people with assembly language background,
not because they need an assembly language programmer, but because they need
someone who can understand computer architecture to write more efficient and more
effective programs.
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5.2 Instruction Formats 5.2 Instruction Formats
Instruction set architectures are measured In designing an instruction set, consideration is
according to: given to:
•  Instruction length.
•  Main memory space occupied by a program.
– Whether short, long, or variable.
•  Instruction complexity.
•  Number of operands.
•  Instruction length (in bits). •  Number of addressable registers.
•  Total number of instructions in the instruction set. •  Memory organization.
– Whether byte- or word addressable.
•  Addressing modes.
– Choose any or all: direct, indirect or indexed.
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5.2 Instruction Formats 5.2 Instruction Formats
•  Byte ordering, or endianness, is another major •  As an example, suppose we have the
architectural consideration. hexadecimal number 12345678.
•  If we have a two-byte integer, the integer may be •  The big endian and little endian arrangements of
stored so that the least significant byte is followed the bytes are shown below.
by the most significant byte or vice versa.
–  Big endian machines store the most significant byte first
(at the lower address).
–  In little endian machines, the least significant byte is
followed by the most significant byte.
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5.2 Instruction Formats 5.2 Instruction Formats
•  Big endian: •  The next consideration for architecture design
–  Is more natural. concerns how the CPU will store data.
–  The sign of the number can be determined by looking at •  We have three choices:
the byte at address offset 0.
1. A stack architecture
–  Strings and integers are stored in the same order.
2. An accumulator architecture
•  Little endian:
3. A general purpose register architecture.
–  Conversion from a 16-bit integer address to a 32-bit
•  In choosing one over the other, the tradeoffs are
integer address does not require any arithmetic.
simplicity (and cost) of hardware design with
–  Makes it easier to place values on non-word boundaries.
execution speed and ease of use.
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5.2 Instruction Formats 5.2 Instruction Formats
•  In a stack architecture, operands are implicitly •  Most systems today are GPR systems.
taken from the stack. •  There are three types:
–  A stack cannot be accessed randomly. –  Memory-memory where two or three operands may be in
•  In an accumulator architecture, one operand of a memory.
binary operation is implicitly in the accumulator. –  Register-memory where at least one operand must be in a
–  One operand is in memory, creating lots of bus traffic. register.
•  In a general purpose register (GPR) architecture, –  Load-store where only the load and store instructions can
registers can be used instead of memory. access memory.
–  Faster than accumulator architecture. •  The number of operands and the number of
–  Efficient implementation for compilers. available registers has a direct affect on instruction
–  Results in longer instructions.
length.
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5.2 Instruction Formats 5.2 Instruction Formats
•  Stack machines use one- and zero-operand •  Stack architectures require us to think about

instructions. arithmetic expressions a little differently.
•  PUSH and POP instructions require a single
•  We are accustomed to writing expressions using infix
memory address operand.
notation, such as: Z = X + Y.
•  PUSH and POP operations involve only the stack’s
•  Stack arithmetic requires that we use postfix notation:
top element.
Z = XY+.
•  Other instructions use operands from the stack
implicitly. –  This is also called reverse Polish notation, (somewhat) in
•  Binary instructions (e.g., ADD, MULT) use the top honor of its Polish inventor, Jan Lukasiewicz (1878 - 1956).
two items on the stack.
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5.2 Instruction Formats 5.2 Instruction Formats
•  The principal advantage of postfix notation is
•  Example: Convert the infix expression (2+3) - 6/3
that parentheses are not used.
to postfix:
•  For example, the infix expression,
Z = (X × Y) + (W × U) The sum 2 + 3 in parentheses takes
2 3+ - 6/3
precedence; we replace the term with
becomes:
2 3 +.
Z = X Y × W U × +
in postfix notation.
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5.2 Instruction Formats 5.2 Instruction Formats
•  Example: Convert the infix expression (2+3) - 6/3 •  Example: Convert the infix expression (2+3) - 6/3
to postfix: to postfix:
The division operator takes next The quotient 6/3 is subtracted from the
2 3 + - 6 3 / 2 3 + 6 3 / -
precedence; we replace 6/3 with sum of 2 + 3, so we move the - operator
6 3 /. to the end.
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5.2 Instruction Formats 5.2 Instruction Formats
•  Example: Use a stack to evaluate the postfix •  Example: Use a stack to evaluate the postfix
expression 2 3 + 6 3 / - : expression 2 3 + 6 3 / - :
2 3 + 6 3 / - Pop the two operands and 2 3 + 6 3 / -
Scanning the expression carry out the operation
from left to right, push indicated by the operator.
operands onto the stack, Push the result back on the
until an operator is found 3 stack.
5
2
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5.2 Instruction Formats 5.2 Instruction Formats
•  Example: Use a stack to evaluate the postfix •  Example: Use a stack to evaluate the postfix
expression 2 3 + 6 3 / - : expression 2 3 + 6 3 / - :
2 3 + 6 3 / -
2 3 + 6 3 / -
Carry out the operation and
Push operands until another
3 push the result.
operator is found.
2
6
5
5
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5.2 Instruction Formats 5.2 Instruction Formats
•  Example: Use a stack to evaluate the postfix
Let’s see how to evaluate an infix expression
expression 2 3 + 6 3 / - :
using different instruction formats.

Finding another operator, 2 3 + 6 3 / - With a three-address ISA, (e.g., mainframes),
carry out the operation and the infix expression,
push the result.
Z = X × Y + W × U
The answer is at the top of
might look like this:
the stack.
MULT R1,X,Y
3
MULT R2,W,U
ADD Z,R1,R2
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5.2 Instruction Formats 5.2 Instruction Formats
•  In a two-address ISA, (e.g., Intel, Motorola), the •  In a one-address ISA, like MARIE, the infix
infix expression, expression,
Z = X × Y + W × U Z = X × Y + W × U
might look like this: looks like this:
LOAD R1,X LOAD X
MULT R1,Y MULT Y
LOAD R2,W STORE TEMP
MULT R2,U Note: One-address LOAD W
ADD R1,R2 ISAs usually MULT U
STORE Z,R1 require one ADD TEMP
operand to be a STORE Z
register.
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5.2 Instruction Formats 5.2 Instruction Formats
•  In a stack ISA, the postfix expression, •  We have seen how instruction length is affected
Z = X Y × W U × + by the number of operands supported by the ISA.
might look like this: •  In any instruction set, not all instructions require
the same number of operands.
PUSH X
PUSH Y •  Operations that require no operands, such as
MULT HALT, necessarily waste some space when fixed-
PUSH W
Note: The result of length instructions are used.
PUSH U
a binary operation
MULT •  One way to recover some of this space is to use
is implicitly stored
ADD expanding opcodes.
on the top of the
POP Z
stack!
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5.2 Instruction Formats 5.2 Instruction Formats
•  A system has 16 registers and 4K of memory. •  If we allow the length of the opcode to vary, we could
•  We need 4 bits to access one of the registers. We create a very rich instruction set:
also need 12 bits for a memory address.
•  If the system is to have 16-bit instructions, we have
two choices for our instructions:
Is there something missing from this instruction set?
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5.2 Instruction Formats 5.2 Instruction Formats
•  Example: Given 8-bit instructions, is it possible to •  With a total of 256 bit patterns required, we can
allow the following to be encoded? exactly encode our instruction set in 8 bits! (256 = 28)
– 3 instructions with two 3-bit operands.
We need:
– 2 instructions with one 4-bit operand.
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– 4 instructions with one 3-bit operand. 3 * 2 *2 = 192 bit patterns for the 3-bit operands
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We need: 2 * 2 = 32 bit patterns for the 4-bit operands
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3 3 4 * 2 = 32 bit patterns for the 3-bit operands
3 * 2 *2 = 192 bit patterns for the 3-bit operands
4 Total: 256 bit patterns.
2 * 2 = 32 bit patterns for the 4-bit operands
3
4 * 2 = 32 bit patterns for the 3-bit operands
One such encoding is shown on the next slide.
Total: 256 bit patterns.
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5.2 Instruction Formats 5.3 Instruction types
Instructions fall into several broad categories
that you should be familiar with:
•  Data movement.
•  Arithmetic.
•  Boolean. Can you think of
•  Bit manipulation. some examples
•  I/O. of each of these?
•  Control transfer.
•  Special purpose.
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5.4 Addressing 5.4 Addressing
•  Addressing modes specify where an operand is •  Immediate addressing is where the data is part of
located. the instruction.
•  They can specify a constant, a register, or a •  Direct addressing is where the address of the
memory location. data is given in the instruction.
•  The actual location of an operand is its effective •  Register addressing is where the data is located
address. in a register.
•  Indirect addressing gives the address of the
•  Certain addressing modes allow us to determine
address of the data in the instruction.
the address of an operand dynamically.
•  Register indirect addressing uses a register to
store the address of the data.
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5.4 Addressing 5.4 Addressing
•  Indexed addressing uses a register (implicitly or •  In stack addressing the operand is assumed to be
explicitly) as an offset (displacement), which is on top of the stack.
added to the address in the operand to determine •  There are many variations to these addressing
the effective address of the data. modes including:
•  Based addressing is similar except that a base –  Indirect indexed.
register is used instead of an index register.
–  Base/offset.
•  The difference between these two is that an index –  Self-relative
register holds an offset relative to the address given
–  Auto increment - decrement.
in the instruction, a base register holds a base
•  We won’t cover these in detail.
address where the address field represents a
displacement from this base.
Let’s look at an example of the principal addressing modes.
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5.4 Addressing 5.4 Addressing
•  For the instruction shown, what value is loaded into •  These are the values loaded into the accumulator
the accumulator for each addressing mode? for each addressing mode.
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