CERN Accelerator School Digital Signal Processing

438 Pages·2008·49.29 MB·English

CERN–2008–003
14March2008
ORGANISATION EUROP(cid:131)ENNE POUR LA RECHERCHE NUCL(cid:131)AIRE
CERN
EUROPEAN ORGANIZATION FOR NUCLEAR RESEARCH
CERN Accelerator School
Digital Signal Processing
Sigtuna, Sweden
31 May–9 June 2007
Proceedings
Editor: D. Brandt
GENEVA
2008
CERN–320copiesprinted–March2008
Abstract
These proceedings present the lectures given at the twenty-first specialized course organized by the
CERN Accelerator School (CAS), the topic being Digital Signal Processing. The course was held in
Sigtuna,Sweden,from31May–9June2007. Thisisthefirsttimethistopichasbeenselectedforaspe-
cialized course. Taking into account the number of related applications currently in use in accelerators
around the world, it was recognized that such a topic should definitively be incorporated into the CAS
seriesofspecializedcourses. Thespecificaimofthecoursewastointroducetheparticipantstotheuse
and programming of Digital Signal Processors (DSPs) and Field Programmable Gate Arrays (FPGAs)
evaluation boards. The course consisted of lectures in the mornings covering fundamental background
knowledge in mathematics, controls theory, design tools, programming hardware platforms, and imple-
mentationdetails. Intheafternoonsthestudentssplitintotwogroupswithpeopleworkinginpairs. One
group worked on problem solving using a PC-based workstation connected to a DSP evaluation board
while the second group performed the same exercise on PCs connected to a FPGA evaluation board.
Half-way through the school, those working on DSPs moved to FPGAs and vice versa. The problems
to be solved were of increasing difficulty and all of them were directly related to real and practical
realizationscurrentlyinuseintheacceleratorfield.
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Foreword
The aim of the CERN Accelerator School (CAS) to collect, preserve and disseminate the knowl-
edgeaccumulatedintheworld’sacceleratorlaboratoriesappliesnotonlytogeneralacceleratorphysics,
but also to related sub-systems, equipment, and technologies. This wider aim is achieved by means of
specializedcourses. For2007,thetopicofthecoursewasDigitalSignalProcessing(DSP)andwasheld
attheSigtunahÃu˝jdenHotel,Sigtuna,Sweden,from31May–9June2007. Thecoursewasorganizedin
collaborationwiththeUppsalaUniversity,Sweden.
ThiswasthefirsttimeDigitalSignalProcessingwasusedasatopicforaCASspecializedcourse.
However,whenconsideringthenumberofrelatedapplicationscurrentlyinuseinthefieldofaccelerators,
itwasfeltthatitwastherighttimetoaddressthisspecifictopic. Theorganizationofsuchacoursewas
arealchallengeinitself,sinceitimpliedfindingandtransportingcomputerstoSweden,negotiatingthe
availability of software licences for the duration of the course, negotiating the acquisition of DSP and
FPGAevaluationboards,andpreparing50computerstobecompatiblewiththeproposedexercises. Itis
a pleasure to express my thanks to CERN, the companies Synplicity, Mathworks and Xilinx, as well as
theTexasInstrumentsWorldwideUniversityProgram,andtheXilinxUniversityProgramfortheirkind
support,withoutwhichthecoursewouldnothavebeenmadepossible.
To ensure that the required material was made available was certainly a mandatory pre-requisite,
but the elaboration of the course and, in particular, the hands-on courses in the afternoon sessions were
nolesschallenging. IwouldparticularlyliketoacknowledgetheoutstandingcontributionofourCERN
colleagues Hermann Schmickler, Maria-Elena Angoletta and Javier Serrano for their contacts with the
relevant industry and the high-quality afternoon courses they prepared and supervised, John Evans for
his hard work in obtaining the software licences and Edwige Bournonville for the perfect preparation
of the computers as well as their maintenance during the course. Similarly, I would like to thank Leif
Gustafsson and Pawel Marciniewski (Uppsala University) for their highly appreciated contribution as
tutorsduringtheafternooncourses.
It is also important to thank the Local Organizing Committee (Professor Tord Ekelof, Dr. Volker
Ziemann and Ms. Inger Ericson) for obtaining financial support from the Swedish Research Council
(Vetenskapsraadet)tohelpCASwiththeorganizationofthecourse.
As always, the backing of the CERN management, the guidance of the CAS Advisory and Pro-
grammeCommittees,theattentiontodetailoftheLocalOrganizingCommitteeandthemanagementand
staffoftheSigtunahÃu˝jdenHotelensuredthattheschoolwasheldunderoptimumconditions.
Very special thanks must go to the lecturers for the enormous task of preparing, presenting, and
writinguptheirtopics.
Finally,theenthusiasmoftheparticipantswhocamefrommorethan23differentcountriesaround
theworldwasconvincingproofoftheusefulnessandsuccessofthecourse.
Itismypleasureandprivilegetothankmostsincerelyallthosepersonswhohelpedmetomakethe
courseasuccess,includingBarbaraStrasser,SuzannevonWartburg,andtheteamoftheCERNScientific
TextProcessingServicefortheirdedicationandcommitmenttotheproductionofthisdocument.
DanielBrandt
CERNAcceleratorSchool
v
Saturday 9 June Buses to airport
February 2007 Friday 8 June Real Time Control of Beam Parameters II M. Dehler Controls Integration II T. Shea A K BI Application II U. Raich Outlook or Seminar H. Schmickler Parallel Lab course (DSP/FPGA) Group B/A Discussion Session D. Brandt A K Parallel Lab course (DSP/FPGA) Group B/A DINNER
Thursday 7 June Real Time Control of Beam Parameters I M. Dehler RF Application II T. Schilcher F F E E B R E Controls Integration I T. Shea BI Application I U. Raich L U N C H Parallel Lab course (DSP/FPGA) Group B/A Parallel Lab course (DSP/FPGA) Group B/A F F E E B R E Parallel Lab course (DSP/FPGA) Group B/A Special Dinner
P) weden Wednesday 6 June Math IV M. Hoffmann RF Application I T. Schilcher C O Transverse Feedbacks M. Lonza Longitudinal Feedbacks M. Lonza Parallel Lab course (DSP/FPGA) Group B/A Parallel Lab course (DSP/FPGA) Group B/A C O Parallel Lab course (DSP/FPGA) Group B/A DINNER
SS
ME sing (Dgtuna, Tuesday 5 June E X C U R S I O N
PROGRAMDigital Signal ProcesMay – 9 June 2007, Si Monday 4 June Math III M. Hoffmann Control Theory III S. Simrock Introduction to DSP III M. Angoletta Introduction to FPGA III J. Serrano From Analog to Digital III J. Belleman Parallel Lab course (DSP/FPGA) Group A/B Parallel Lab course (DSP/FPGA) Group B/A DINNER
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3 e e
Sunday 3 June Math II M. Hoffmann Control Theory II S. Simrock R E A K Introduction to DSP II M. Angoletta Introduction to FPGA II J. Serrano H From Analog to Digital II J. Belleman Parallel Lab cours(DSP/FPGA) Group A/B R E A K Parallel Lab cours(DSP/FPGA) Group A/B DINNER
Saturday 2 June Math I M. Hoffmann Control Theory I S. Simrock C O F F E E B Introduction to DSP I M. Angoletta Introduction to FPGA I J. Serrano L U N C From Analog to Digital I J. Belleman Parallel Lab course (DSP/FPGA) Group A/B C O F F E E B Parallel Lab course (DSP/FPGA) Group A/B DINNER
Friday 1 June Types of Accelerators and Specific Needs I T. Shea Types of Accelerators and Specific Needs II T. Shea High Level Modeling Tools I J. Evans High Level Modeling Tools II J. Evans Introduction to Afternoon Courses H. Schmickler Parallel Lab course (DSP/FPGA) Group A/B Parallel Lab course (DSP/FPGA) Group A/B Welcome Drink
me 30 30 30 30 00 00 00 00 30 30 30 30 00 00 00
Ti 08: 09:09: 10: 11: 12:12: 13: 14: 15:15: 16: 17: 18:19:
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Contents
Foreword
D.Brandt ................................................................................ v
High-levelmodellinglanguages
J.Evans .................................................................................. 1
Digitalsignalprocessingmathematics
M.Hoffmann ............................................................................ 11
Controltheory
S.Simrock ............................................................................... 73
Fromanalogtodigital
J.Belleman ............................................................................ 131
Digitalsignalprocessorfundamentalsandsystemdesign
M.E.Angoletta ......................................................................... 167
IntroductiontoFPGAdesign
J.Serrano .............................................................................. 231
RFapplicationsindigitalsignalprocessing
T.Schilcher ............................................................................ 249
Multi-bunchfeedbacksystems
M.Lonza ............................................................................... 285
Realtimecontrolofbeamparameters
M.Dehler .............................................................................. 331
Beamdiagnostics
U.Raich ............................................................................... 361
Controlsystemintegration
T.J.Shea ............................................................................... 385
LHCtechnologicalchallenges: useofdigitalsignalprocessorsinthepowerconvertersfortheLHC
particleaccelerator
H.Schmickler .......................................................................... 411
ListofParticipants ........................................................................ 429
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High-level modelling languages
J. Evans
CERN, Geneva, Switzerland
Abstract
This paper gives an introduction to the latest developments in modern
electronic design methodology. It will give a brief history of the evolution
of design software in an attempt to explain the seemingly haphazard
development up to the present-day situation.
1 Introduction
This paper gives an introduction to the latest developments in modern electronic design methodology.
It will give a brief history of the evolution of design software in an attempt to explain the seemingly
haphazard development of these tools to become what is now known as the Electronic Design
Automation industry. The emphasis is to provide a common background to all school attendees with
specific references made to the tools used during the week.

The frenetic pace of advance in the electronics industry is not expected to change in the near
future. According to the research firm Gartner, there is no slowdown in the expected revenue growth
for the Field Programmable Gate Array, Application-Specific Integrated Circuit and Application-
Specific Standard Product markets for the next few years [1]. FPGAs look set to maintain the highest
compound annual growth rate (almost 20%) as more and more applications adopt this solution due to
their increasing functionality and decreasing costs and the often prohibitive development costs for
ASICs and ASSPs. (ASSPs are essentially ASICs dedicated to a specific application market and sold
to more than one user.) The total 2007 revenue from three families is expected to reach almost 100
billion US dollars.
Modern-day electronic design tools have evolved for a very good reason. The increasing size,
speed, and complexity of these new products and the increasing pressure on bringing them to market
quickly means that design targets would be impossible to reach without help from software programs.
Tool development has been continuous over the last thirty years. What traditionally was based
on the two main axes of analog or digital designs has now been expanded to include software additions
and we shall see how these previously distinct areas are becoming increasingly blurred and merging.
1.1 A brief history
Before electronic design automation, PCBs were designed by hand and manually laid out. Perhaps
more surprisingly, this was also true for IC design. The first programs developed were drafting
software that included some digitizing capabilities with different companies focusing on specific areas
of the market. Calma was a major player in the area of IC manufacture (its GDSII format still exists)
while other essentially similar products targeted the PCB sector. While invaluable in laying out a
board or IC, there was still no link between the design process and the eventual layout. Various large
companies developed their own in-house software and methodology solutions and some of these teams
were eventually spun out as separate companies in the beginning of the 1980s. Various pioneers of the
EDA industry date from this period: Mentor Graphics (original parent company Tektronix), Daisy
Systems (Intel) and the forerunner of Cadence Design Systems, Valid Logic Systems (spawned from
Hewlett Packard and the Lawrence Livermore Laboratory).
1
J. EVANS
The need to simulate the transistors being laid out for all ICs was one of the inspirations for the
development of the Simulation Program with Integrated Circuit Emphasis (SPICE) software at the
University of California, Berkeley. The main driving forces behind the original SPICE program are
credited to Larry Nagel working under the supervision of Donald Pederson. The work was based on
the CANCER program and was one of the many such projects funded by the United States Department
of Defense. Pederson insisted that the newly written SPICE be far enough removed from the original
CANCER such that any distribution restrictions could be removed and that the program be put in the
public domain.
The first public presentation of SPICE1 at a conference was in 1973 [2]. This was a relatively
limited-feature program based on nodal analysis (leading to problems in describing some circuit
elements, particularly inductors) and fixed time-step transient analysis (this aspect will be discussed in
more detail later in this paper). SPICE2 was introduced in 1975 and offered improvements such as
more inherent circuit elements, variable time-step analysis, and solutions based on modified nodal
analysis. These were significant advances and ultimately led to the program’s widespread adoption.
SPICE2 was further developed until 1983 with the introduction of SPICE 2g6 which was the last
FORTRAN version of the program. SPICE3 was written in C and was introduced in 1989.
The insistence on SPICE’s open-source development (and famously, program availability for
the cost of a magnetic tape) led to its becoming widely distributed and used as the basis for countless
other simulators in the academic, industrial, and commercial worlds. Well-known commercial
versions still existing today include HSPICE (now owned by Synopsys) and PSpice (currently owned
by Cadence Design Systems).
Most ‘digital’ design tools also being developed during the same period were largely based on
schematic-driven design entry. One of the next major advances was the development of text-based
Hardware Description Languages (HDLs) describing design behaviour at the Register Transfer Level.
RTL describes the operation of synchronous digital circuits where signals are treated before being
clocked into hardware registers. HDLs allowing circuits to be described using RTL provide a much
higher level of abstraction than at transistor or at gate level. Since the strengths and advantages of this
level of abstraction were realized, tools were subsequently developed to allow direct and automatic
gate synthesis from the HDL circuit description. This was a major step forward in the EDA industry
and allowed a huge advance in design complexity and reduced time to market.
Two major HDLs became prominent during the mid-80s.
Verilog is a proprietary language defined by Gateway Design Automation. This was an
industry changer and is still the prominent language in certain design areas. Written by Phil Moorby
in around a year, it quickly became the de facto standard for ASIC design along with the Verilog-XL
simulator. Its impact was reinforced when Synopsys introduced software permitting direct gate-level
synthesis from the Verilog netlist. This allowed a direct line from design description to simulation and
layout in one integrated flow. Gateway was eventually acquired by Cadence Design Systems during
1989. With the increasing market penetration of VHDL (described below), Cadence decided to make
the language generally available through the Open Verilog International organization. The language
was later submitted to the IEEE for standardization and this was eventually accorded as IEEE Standard
1364-1995. Subsequent developments of Verilog have culminated with the release of SystemVerilog.
The Very-High-Speed Integrated Circuits Hardware Description Language (commonly
abbreviated to VHDL) was developed for the United States Department of Defense. It was becoming
impossible to reproduce reliably the functionality of technically obsolete equipment as its
specifications were insufficiently documented. VHDL was conceived as an attempt to overcome this
limitation by defining a language that could formally and completely describe an object’s
specification. It was based on the existing ADA language syntax so as to benefit from already well-
proven concepts. As with Verilog, the idea of being immediately able to simulate and synthesize the
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