(Cascaded 4 Bits) Dual Slope ADC

40 Pages·2016·3.26 MB·English

Daniel Andorful

An 8 Bit (Cascaded 4 Bits) Dual Slope ADC

Helsinki Metropolia University of Applied Sciences

Bachelor of Engineering in Electronics

Thesis

2016
Abstract

Author(s) Andorful Daniel
Title An 8 Bit Dual slope ADC Using TWO(2) cascaded 4 Bit counters

Number of Pages 34 pages + 2 appendices
Date 23rd May 2016

Degree Bachelor of Engineering

Degree Programme Electronics

Instructor(s) Heikki Valmu, Senior Lecturer

The purpose of this thesis was to create and understand the use of a dual slope ADC
using Two (2) 4 Bits cascaded counters.

During the process of this thesis, both a simulation and actual laboratory works were done
to compare and verify the operations as compared to the theory being investigated. The
making of this Dual Slope ADC was first done by creating the various parts of operation in
pieces to check they function before finally putting them all together. This design was first
done with the help of MULTISM simulation tool where all the design was made and the use
of Ultiboard to print out the PCB layout with the 3D view.

After the simulation was done to check for errors and it efficiency, the design was made in
the Laboratory and various measurements are taken. With the help of the data collected in
the Lab, one was able to determine the operation of the Dual slope ADC.

The conclusion of the study showed the efficiency of the Dual slope ADC as compared to
other ADCs, most especially the Single slope ADC

Keywords Dual slope, ADC, 8 bit, counter, cascaded 4 bit
Contents

1. Introduction ........................................................................... 1

1.1 Background ........................................................................ 1

1.2 Relevance Of The Thesis ................................................... 2
.
1.3 Introduction To Thesis ........................................................ 3

2. Classroom Input And Theoretical Background .......................... 4

2.1 Dual Slope Converters ........................................................ 4
AD/DA Convertors ..................................................................... 8
2.2 Comparators....................................................................... 8
2.2 Sample And Hold............................................................... 9
2.3 Time Quantization ............................................................ 10
2.4 Quantisation Noise ....................................................... 10
2.5 Signal-To-Noise Ratio (SNR)………………………............ 10

3. Types Of A/D,D/A Convertors .................................................. 11

4. Methodology ............................................................................ 17

5. Equipment ................................................................................ 21

5.1 IRF510 MOSFET (Enhancement ) .................................. 21
5.2 LM741 Operational Amplifier ........................................... 22
5.3 74LS191 4 Bit Counter .................................................... 23
5.4 7404 Inverter .................................................................. 24

6. Measurements ......................................................................... 25
6.1 counter 34 ...................................................................... 25
6.2 The switch 35 ................................................................. 26
6.3 J_K flip flop 36 ............................................................... 27
6.4 Complete Circuit ............................................................. 28
6.5 Circuit layout and 3D representation .............................. 30

7. Conclusion ................................................................................ 32

8. Reference

Appendices

Appendix 1.

Appendix 2. Lab Setup
Abbreviations

MOSFET: Metal Oxide Field Effect Transistor

PCB: Printed Circuit Board

ADC: Analog to Digital converter

DAC: Digital to Analog converter

V : Input Voltage
in
V : Reference Voltage
ref

MSB: Most Significant Bit

LSB: Least significant Bit

SNR: Signal to Noise Ratio

OPAMP: Operational Amplifier

RMS: Root Mean Square

F : Sample Frequency
sample
1

1 Introduction

1.1 Background

This thesis takes into consideration the Analog to Digital converters more especially,
the Dual slope Analog to digital converter.
The purpose of this work was to understudy the functionalities as well as the operations
of the various converters (AD/DA converters) with emphasis laid on the Dual Slope
ADCs.
The main purpose was to construct a 16bit Dual Slope AD converter with an input
voltage of 5V.
The construction of these various converters was first done using a simulation tool
known as MULTISM 12.0 and this generates the expected various results required. A
counter of frequency 1KHz was constructed in the simulation as it was used for the
timing of the switches.
After the result is gained, the converters were then built using the Mentor graphics (Pad
logic and Layout) to design the board and then the board milled with components place
on it.
The final Printed Circuit Board (PCB) was then calibrated with the clocking of the
switches done manually this time and the various resulted tabulated and compared to
the simulated version to check for accuracy.
2

1.2 Relevance of the thesis topic

The Dual slope ADC is an analog-to-digital converter that does its conversion using
quite low bandwidth as its input. Though the operation is quite slow, it has the ability to
reject high frequency noise. It is very much useful in industrial environment that have a
lot of noise by providing a good resolution when used within a fixed frequency of 50Hz
and 60Hz.
The use of low current supply makes it quite adequate for use in various forms.
This technique of conversion helps do away most of the problems associated with
capacitor and comparator. It also has the ability to achieve a good accuracy without
having to put extreme requirements on the components stability.
Dual slope conversion is very much preferred in precise digital multi-meters, and also in
10-bit to 18-bit conversion modules.
Its ability to give a good and accurate results, high stability at the low cost, and an
excellent rejection of interference (eg. power-line), for applications where speed is less
required makes it quite relevant for this thesis.
3

1.3 Introduction to the thesis topic

There are many ways of converting Analog signals to Digital (voltage or current). But
Dual slope conversion shows to be quite good when it comes to the precision
resistance, eliminating noise and good stability at a low cost makes it use quite efficient
and acceptable.
An input voltage which is proportional to the current (level) has to charge a capacitor for
a fixed time (period) t. After it has been charged within the time interval, t, a reference
voltage with an opposite polarity was applied to the integrator input when the device
resets it counter. The capacitor was discharged with a constant current so that the
voltage reaches "ZERO", ones the opposite polarity signal is applied. The time for the
capacitor to discharge was seen to be proportional to the input voltage and this enables
the counter which is also driven from a clock running at a specific frequency[6].
The Dual slope ADC seems more convenient for standard measurement in 4-digits
resolution.
In this thesis, two 74LS191 ICs were used with the IRF510 MOSFETs.
4

2 CLASSROOM INPUT AND THEORETICAL BACKGROUND

2.1 Dual-Slope Converters
This is an approach used for very good precision low-speed analog-to-digital conversion.
The input voltage signal is used to charge the capacitor so that its voltage reaches a fixed
threshold. Then the digitally created circuit measures the time needed to reach its threshold
by means of counting the pulses generated from a fixed-frequency clock[3,7].
This type of conversion can be used often where there is the need for high resolution but
slow, low-precision converters because very little components are required.
It has two major parts: first, the circuit which digitalizes the acquired input thereby producing
a pulse phase sequence and the other, the counter(N-bit) which converts the result into a
digital value[1,2].

Figure 1 Dual slope setup model [1]

With this kind of conversion, there is the need for accuracy in the components
measurements so as to get the precise results needed.

Working principle
The working process requires the use of the input voltage to charge the capacitor for a fixed
time period. The capacitor's reference voltage discharges the capacitor and the digital
control circuit measures the time for the capacitor to discharge completely. The ratio of the
discharge time to the charging time is the ratio of the unknown to the known voltage[ (7),3].
5
This conversion type operates independently of its integrator component's values, due to the
fact that charging and discharging is done by the same circuit.

Figure 2 Dual slope conversion cycle [ (7)]

The Dual slope ADC circuit, is made up of a switch, an integrator, a timer showing the
needed time when the unknown voltage is integrated the unknown and measures the
reference voltage timing as well as the controller, and a comparator. The switch should be
placed between the voltage measured and the reference voltage (negative). Based on the
kind of operation, resetting the integrator, thus by discharging is done by a parallel
connection of the integrator capacitor.
This Dual slope conversion has two phases; the run-up also referred to as the 'counting up'
phase and the run-down phase(counting down). During run-up, the voltage supplied to the
integrator is measured. At which point, the input voltage provided to the integrator which is
selected by the switch is measured. The integrator is then allowed to ramp for a fixed
interval of time for the charging of the capacitor. For the run-down phase, an input to the
integrator is in the form of a negative reference voltage [ (1),5], the switch then chooses this
6
reference voltage to be its input voltage of the integrator. The time taken for the integrator's
output to return to zero value is measured during this phase.

At constant input, integrator can be shown by equation 1, given as:[2]

(cid:2906)(cid:2919)(cid:2924)
V =− tint+Vint .............................................................. (1)
out
(cid:2902)(cid:2887)

If the integrator voltage initially at the beginning of each conversion is zero and that at the
end of the run down period will be zero, these equations represents(equation 2 and 3) the
two phases:

(cid:2906)(cid:2919)(cid:2924)
V = - tu ..................................................................... (2)
out-up
(cid:2902)(cid:2887)

(cid:2906)(cid:2928)(cid:2915)(cid:2916)
V = -− td+Vout−up=0 ....................................... (3)
out-down
(cid:2902)(cid:2887)

Solving we get:
(cid:1820)(cid:3031)
V = - V ............................................................................. (4)
in ref
(cid:1820)(cid:3048)
Where V is the output voltage
out
V is the reference voltage
ref
V , the input voltage
in
R and C, resistor and capacitor respectively
V , output voltage during up ramp
out-up
V , output voltage during down ramp
out-down
V , the initial voltage supplied
initial
t , Initial time
int
t , time during ramp up stage
u
t , time during ramp down stage
d