BSTJ 60: 7. September 1981: Digital Signal Processor: Logic and Fault Simulations. (Eldumiati, I.I.; Gadenz, R.N.)

5.6 MB·English

Digital Signal Processor:

Logic and Fault Simulations

By LL ELOUMIATI and R. N. GADENZ
(anus ecvet Oacomber 3, 1860)

This paper illustrates a methodology for the design verfiation
cand testing of the Hell System algitad signal processor. [is shown
that @ behavioral approach, as opposed ton structural approach, (8
aadvantogeous far the generation of fst se! of fst vettors, since
thie sot () exercises all the fimetions, us they ure specified by the
instruction st, an fi) uncovers the bulk of the faults. The sot cam
‘then be proce using the structural approach. The participation of
‘the device destgners inthis process i essential. The relation Betsren
fault coverage and yield is also discussed. Thersical relations are
fiven which shove how important i ts have w high font! coverage
fsa, =85 percent) for vest chips

1. INTRODUCTION

In this paper, we describe the loge simulation a! ful aruysis of
programmable W131 digit signal processor (ose) develope by Ba
Leboratorien The design of virh complex ineegrated circuit requires
an extensive effort in the areas of design verification, testability, and
fue coverage. Such an effort hne x considerable impact upon the
‘lesign cycle sila and reliability of the device

In the following section we discuss dosien verification, which was
done in sefeware through computer simlations. Seeton TIT presents
testing and the associated problem of xenerating test vectors, Come
puter simulations of the faulted eicut allow us to determine the fal
overage obtainable with a set of mpur vectors. The reliion between,
fault coverage and true yield ie diacuseed in Section TV
1. DESIGN VERIFICATION

“The design verification of vist logic ere could be done eicher it
software viv a curate model of in huelware by building a brea
boar, or in bth, The software appech i easier to setup and more
exible to use and tof. On the other bund, ence bu, a breadboard
fean bo weed it only for desi werifcation but also for realtime
testing un che development of support hardware. Barly users an as
benefit from it for ther inilol system design. However, a hardware
‘movel i usually built with ssf and atsi components an requires
therefore, an adaptation of the orginal cixeuit. The breadboard could
be constructed oo thal i nflects the state of the circuit an a clock
tycle basi, but itis very dificult to emulate dymamic structures snd
bus precharze circuits As oul, design problems resulting from che
tse of such ennfgurations may be used in ¢ breadboard,

‘Computer model for VLst design veriication may be o functional
Aegeription in & high-level lenguege, uch a2 ADLIn," a gate level
(exertion asin tan, ora trunnion level representation usin MOTIS"
land srror.” Functional analss provides s coarse simlation end its
tice is limited to the initial stages of the device conception. On The
ther hand, a tianestor level eeeripcion ia quice complex alex
Tis meat useful for the analysi of eiical timing patha, A gate level
eeciption can be ucilized both for sign werGeation and feult
fsnaljsis, A furiher advantage is that il ca slko he used direc for
futomatic muting, a8 in LI during chip layout. Computer aided
futomate rong ean use forthe youl of several ps sections chal
have relaxed performance requirements,

Tn the design verfemion of ue nse. a functional detciption Iut-
gvage was une ao preliminary check Rr sone particulnly complex
ivliona. ame was worl Chroughout the design pha of the deviee,
frst to verify the lgircesign of the individual setion® wn then 0
Fimnulave the complace devies, In its final form, the LAMP computer
model uses gate level description Tor the random logic section, hich
Consists of approximately 1400) transiators and a functional descrip=
tion for the memories, moTTS nnd suey. were eleo extensively used to
Analyze the behavior ofthe \ime-eiteal portions of the device.

Figure 1 illusester the LAMP structure. ‘The souree file for the
computer rwtel i waite i Tanguage known as Tstnt0caL (a
Combination af Loge Simulation Language and Losie Circuit Analyzer
Caryunge. "The sume description ean be ws for woras and rx. The
Use ofa common sree language forthe Toye and timing simulator,

‘well as the sulomstic router, has an obvious advantage towarl
fenerating an error fee layout, The L81-L0CAL. provide a description
bf the various cireuit enmponants aad their incerconnections, using
Standard Togie gates and, whenever possible, a ibrar of NOs subnet

1464 THE RELL SYSTEM TECIINIGAL JOURNAL, SEPTEMBER 1961
svorks or polycell. xan transforms this desription into an objec fle
‘which isa tf trth ible

"The Las true-valuesmlator uses the truth tables combined with
‘asstof input vector to cheek the behavior ofthe eieuit under aera
‘orunfauled coalitions, ach ast vector specifies a set of values (Lor
0} atthe circuit inpucs for etch clock phase. Gave delays aze uniform
{nitary)theoughoot the cireuit. zero gate delay ean abs be apeeife
to beter simulate the structural Behasinr of romplex cell, For exch,
vveewor, LauP simulates the propegstion of signals from inputs 10
fuspucs Taking time stepe equivalent to the unitary gate delay. By
texatuning the value ofthe outpat egal, which are elther 0, 1 or 3
(don't know"), ite posible co verify the gate level perfomance of
the circuit, aswell s identify long circuit paths, races, and osiations
‘An oscilation is declared if an output doesnot eetle within prudent
‘nurbor of time stops spuifed by the use.

"The diagram in Tig. 2 outlines the atepe followed in the design
verification precedure for the usr. Once the resulta af che erve value
‘mulation wore sulisfatory, iming simulations were carried out boch
fon Moris and. spice, Moms war ueed v0 check the overall ming
performance of the random logic portion of the mst (approximately
T4Q00 Ininsistors. SIC similation wna extensively eed in areas

LOGIC ANO FAULT SMULATIONS 1465:
“where che device performance had ctical cing muiemencs. These
include thy presane clocking sytem, che bus interZace and precharge
Sreutry, cxileal patha with Tong delays or excessive loading, snd
places where races may occur, Dovng the initial stages of layout, che
tiring stat ioe ucized estimated vale of the parasites: actual
Values were substituted at a later stage when needed.

UM TESTING ANO FAULT ANALYSIS:

‘The vse architectute fciilales testability and program develop-
‘ment. The Dar i customized (o perform signal processing functions by
deans of un tivehip nuat which slores both program al fixed data,
However, the ability to aocse an external Row is also provided. This
fruernal memory interfree featur allows emulaing the DSP program.
fand provides a means for device esting. Address information and data
fare multiplexed om tho external bus pins, with hand ahalking sigan
Indicating the presence of address or nee! for date. Thea signals
nko be used by an autonatietetartoeicher force an input voctor or
‘compare outpat data, Ta addition, to help in the debugging provers,
the ehip layout was partitioned and internal pads were provided, Uns

a

1406 THE BELL SYSTEM TECHNICAL JOURNAL, SEPTEMBER 1951
allowing the posiilityof independent exercising and testing each of
‘the ose sections

‘he input vector needed fo design verification were elected so as
tw exereae all bs functions, which ave specified by the inetruclion st
"These functions were combined with data sears of ether alternating
sero el ones and their complements, or apeife dats pallerae for
functions that exhibit a known pattem sensicivty. The task of gener
ating the vectors was further simplified by che use ofthe per Asem:
bler, which eenalaten a functional input inka machine cae and deals
‘with some specific archteerural features ofthe Ds, such as pipelining
‘and skewing of estan instruction fields, Tn aon, using ls bh
‘oral or Tanetional approach, the expected outputs were easly pre
dicted, Tn summary, this approach vo generate the vectors required for
‘design verification proved adequate,

"The same set of vectors served an inl input to Lau for the
Faull sirmlations and wat able to detect che bul of the faults. As
result t Became the main portion of the test vectors subsoquentiy
vse for teating the bse devices. Recently, Seygenda staggered that it
seems reasonable (o expect thal this procedure wil be successfl” Our
fxperienoe confirma that this isthe caso, Thus, we believe that che
Teliioral appl to law vector generation isto be preferred to che
structural approach, atleast an it step, The lacter approceh eis
it senaitining each node ofthe cteut and propagating the eects to
‘the ourpurs, using a set of vectors which may not represent necessary
meaningfl device Functions. The process is both longtny and costly.
Carrontly availale programs for automate tat generstion (each as
the AG feature of CAMP or Terie’ PA aze also bazed on the
structural approach; as result, they are limited in capability and
‘expensive to use, eepovialy for devices with auch complesty g= che

"The faults exercised in LAMP are gave inputs and outputs stuck at
cither 2am oF one, with che excitation und alservtion points being at
‘the png. For each input vector, taMP eansiersone fat ata ie and
‘ompares che outputs ofthe faulted and unfaultedeiruit. A faut
detected if a change is observed at the uu pins. Pauls that have
‘equivalent effects on che output g26 collspeed i order to resice
‘ompatetional cot. Also, once a faulc has been dececed, ii posible
to remove ie fom the lit of faults, en chat che fllowing vectors will
‘not have to conser it, The Lan simulation provider lst of wl test
Insstd (ath) fale, us well se information on paaible races and
seillatons caused by the faults. From thee data, the fault coverage
and subsequent steps to improve it esn be determined.

‘Figure 3 ispige the fault coverage given by vat versus che
nsaber of last veclone used to very the Ds random loi. ‘The feult,

LOGIC AND FAULI SINULATIONS 1487
coverage achiovell with ~9000 vectors generated via the behavioral
fppvoach was #82 percent, This i= an excellenceteting point in che
{qt for w high fault coverage, Our goal was to obtain a fl average
ib exceos of 6 percent. Anilysis of the undetocted faults and the
structures wed ithe eireuitimplemencatin reveue that the actus)
fault covernge i significantly higher than the valav given hy ‘am
"Thies because faults no observable die to built-in irc. redundan-
cles an be disregarded along wth the falta which are ot dete in
the simulator bur willbe decetel in the actual crea, The na ining
Delzes 0 foursphase clock wih non-overlapping master and slave
Dulets in each phase ‘Those pulss are ueed (achieve signal transfers
Tetween registers The wer ant slave pues are generated locally
in each of the Dar sorts, and are kept synchronous through &
Universal ynchronising signal. This clocking slime is tolerant
tori clases of fault sich a stuck laves ifthe data synchronous
When relocking is dane tthe boundavis of the ner sections, some
fiulus may’ be disregarded if src simulation indieate proper timina—
ft those houndaries Other examples of faults that can he neglected,
tre the oes reauling in setehed depletion loads being aay on, if
the device meets the maximum power Mssipation requirement, sal
the undetected faults that are duo 19 naseighed instruction fields

"To tchiewe high reliability, the test vectore shoul guurantee sn
extensivo fault coverage whith should cover not only Une device
funecons, but alas the structures used for Ue cre mplementation.
"This especially important beeauae the DsP is peogearamable and
test vectore are designed to be independent of Ue program in the on

1460 THE BELL SYSTEM TECHNICAL JOUIMMAL, SEPTEMBER +981
chip nom ve avoid costly test program development. A more in-tepth
Took atthe cevnit was rune en detect at lout part ofthe remaining
feclls and further improve the fn coverage beyond 6 percent
Adiitional specie sequences of tex vecurs hl ta he generated bs
rans of « alructural approach. These sequences were applieg 0
browse the faulte not previously develo and to propagate their
tffecs to Lhe eta pins

"The vectors use tae the neP random loge exercise ony a Limited
jpumber of naw locations. Therefore, the Rant further tasted by
Ivcing inka tad reading from it standard checkerboard patterns.

sceurulated into achecksum which stent he outpat-and compared,
‘with the expected value. The coments of the on-chip RoM i alsa
‘verified via checksum lest. The nsP extemal memory interface makes

it possible to trent the contents of the intro Rost ws lata which
fecched eequentilly to compute che checksum. The reli velco
the output where iin compared with the peccaleulated valve, deter-
‘ined rom the user's program, This value the only difference inthe
Camplete testing patiorss of slieent sea The additional vectors
eau to tet he RASK (3600) and the kus (~400) bri ue tute
Ihumber of test weolons sed for the ose to slightly ubowe
20K.

1W, FAULT COVERAGE AND YIELD

‘The fault coverage provides a measure of the fraction ofthe faults
nected by a given ac of (et vectors. A fait eoveruge les than 100,
ppereenc implies thus sine devices which pasted the lest ay Tall to
brccute the user's program. ‘This could be the resalt of usc certain
program eequences oF data patterns that exercise fale nodes not
overed by the ts! vectors. ‘The presence of such devices affets the
feliablity and the eventual cost ofthe host systems Mnliyingfauley
tleviece during incoming inapeccon, any, ur during sem suaseens
bly has sia impacto the cose, Pie inthe field resulta noe ony
fn reduces spatern reliability, But also in higher replacement coat
fd the posable of loss of servien, Therefore, is Very important to
identity faulty devices as mach ax pore during device testing. Tn
Unie mation, the rlacionships among yield, fault coverago, and ehip
area are diseed

‘The reduction in w wafer veld y can be attributed co wu suurves
“Th fees one i che wxistence of area defects, Le, defects that rause
‘whole potions of a wale lo provide no good devices. This area defect
‘ondition ie represented by the parameter in the equation below:
"The second source isthe existence of fal point defocte which are
randomly disibuted over the Wafer area where good chips cum be

LOGIC AND FAULT SIMULATIONS 1469,
the area defect yield factor,
the point defeet densiey, and
the chip active area.

In order vo account for che spread of the vandom defect density D

ing water, Murphy? geste that the defect density is diseibted
secorting toa probability density function. Assuring a game dite
Dution for the defect density D, the average yield, foru vary large
numberof wafers is given by?"

a oe
Tea °

where
Yo dhe average area defect yield factor,
Dy the average value of the detect density, and

A= she variance ofthe defect donsity

It hoa be noted chat the gamma distribution provides the hes it to
experimental yield data To addition, depending on the value of t
fencompnstes several dideibutions whieh were proposed witlier. (ee
ofa & and 11 to 1) Therefore, eq 2 will he used to shady che
relationship betweun fall coverage ntl yield

‘A fault coverage less than 100 percent indicates a lack of observable
exercise for some ofthe Inge gates malking up the circu. Asuing a
fnifarm disinbution of loge gates over the chip active area, che
‘fective chip ates 4, being probed can be expronsed a8 fanetion of
the fault coverage es follows,

ayaa, co)

where Fis the factional fault coverage for 8 given set of tst vectors
‘The ratio berween the troe yield ¥,, obtainable with a 100 percent
fault caverage, andthe yield at probe ¥, ie chen given by

x

= + ABDNAY AL + ADA @

‘Thia expresion can be used to determine the fault coveraxe required
toachieve a desired value for Y/Y

1470 THE BELL SYSTEM TECHNICAL JOURNAL, SEPTEMBER 1067
(FAY + ADNAN =
XDA

“The dependence of the yield on the fault coverage fr several values
of Rand « Dy-A of 3, diaplaved in Table 1

‘The parameter ) is « Gunction of the fabriation facility and could
be determined fromthe yield data, For siapliiy, sme that in the
limit \ auproaches tera. Ten eg, ¥ reduces to

F 8)

ve neo, ei

and eq, 6 becomes
14%

pee iin dt
ma" y,

a

"This expression is plowed in Fig. 4 for eanious values of DA. The
figure emphasizes the iced for extensive fault coverage as the value of
Dye ig increased, For example i order to achieve a value of 09 for
¥i/Yoand assuming a valve of £0 for Dy, the fault coverage ehould
be9885 percent.

. CONCLUSIONS.
‘A methodology forthe design verification, fault anulyse and vesting
cof programmutle wt device va presence. Logie design verification
teas performed atthe gace level through TM ceuevalue sinulacons
‘Stetavof the device having criti lining requltements were verified
vn Moms and sete
"A behavioral spprowsh to test vector generation, ip which all he
‘tevice functions were exercised with appropriate data, proved ade
‘uate for the design verification. Through fault analysis, i was fond
these vectors alan uncovered the bulk of the faults uh berfine,
could be used for sting the device. The structural approach, which i
both lengthy and costly, mas uaed only to generate additional vectra
in onder lo further improve the fault coverage
"The need for an extensive fault coverage, nnd its impact an the
device cost aid rishi, wae emphasized. A relationship between

Table Y/Y, ¥8 Ffor Dos = 3

male

LOGIC AND FAULT SIMULATIONS 1471
?

Fig 4a ene atin of YY a

Faull coverage sil and chip area sas etablished. The analyia show
‘that ii important vo have a fault coverage in excess of 95 percent for
chico lnge areas,

Vi. ACKNOWLEDGMENTS
"The autre wish to thak J, Bodie, N. J Bias, H, Shichenan,

D.C. Seanzione, and RL, Wadstek for useful discussions and com

etl

REFERENCES

1. Hie “Nl Prone Arce wn Heoue

472 THE BELL SYSTEM TECHNICAL JOURNAL, SEPTEMBER 1851