BSTJ 60: 7. September 1981: Digital Signal Processor: An Overview of the Silicon Very- Large-Scale-Integration Implementation. (Barber, F.E.; Bartoli, T.J.; Freyman, R.L.; Grant, J.A.; Kane, J.; Kershaw, R.N.)

3.4 MB·English

Digital Signal Processor:

An Overview of the Silicon
Very-Large-Scale-Integration Implementation

6y F. E. BARBER, T. J. BARTOLI, RL FREYMAN, J. A. GRANT,
“KANE ano AN. KERSHAW

(atanueept eceved July 14, 1980)

A programmatie digital signal processor integrated circuit hos
been designed as & gonera-purpose building block for a variety of
Uclcommunication applications, The device, noun as digital signal
[provessor, tea ingle-chipinlegrobeleireul fabricated in depletion-
load ses technology andl packoxd in a Opin re. This paper
‘describes the silcnn tory-dange-seninintegration (ist) implementa

tion of the digital sant processor with emphasis on the circuit
design phase, The specific anean dscuased are choice of fabrication
technology, layout styles, eieuit design procedures, and circuit cn

siderations

1. INTRODUCTION

A single-chip intgrated circuit hs nn developed asa stand-alone
pur for digital signal processing, Thix device known a cig signal
Processor (nse) functions as a spel purpose microcomputer whose
instruction set, arthmote fonelins, and addressing capability are
‘optimized fr veal-cime signal procesing The primary sections of the
De are a read only memory (ROM), random acceso memory (RAM),
fn address aridhmetie unit (aac, an arithmetic unit (AU), system
‘controle, and appropriate input/output (i/o) excite.

"The RoM i organized ae 1024 words hy Ii-bite persword memory for
ring the system progeamns and fixed det, The aay ie organized as
128 words by 20 hits per word and is used for storage of varable daca
and temporary results. The AAW xenerates the addeaoes forthe RAM.
—
— cach 8140

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Fig Intested art snpameattio rt

sind most, a well a the addnetses Loran enteral wom, The at perforas
the necessary arithmede operationa for digital signal processing
16 by d-bit mulipliation and O-bit accumulation ‘he 70 uni wil
faocopt and genorete« serial bitstream of either «-255 law or linear
‘ost signal samples, The control unit decodas instructions and provides
overall system coordination

Figure 1 shows the proces of implementing the DSP ae an integrated
‘ici, Phin process is divided into w design stage and a Sabrietion
stage. The design stage consiss of four design areas. system, logic
cvuit and layout, In the eaee of the TAP, the aystem design ithe
process of defining the eystem architecture and instruction set! The
loge design assembles logic functions which meet the system's requir
‘ments, The circuit design implements the logic design with electrical
‘deviesso that the systems roqurements are achieved, The fabrication
ofthe integrated cireuit starts with w eircit layout, whichis the end
Teste of the crit design, The crcl! Iaynut used tn proace masks
Which are used in wafer fabrication to define the electrical devices,
‘The completed wafers are tested to devermine good devices that aze
then packaged. The completed integrated cicuits are tasted to verify
that the system requirements are met

‘This paper desenbesthe circuit design phase ofthe integrated circuit
lmplementation of the Ds.

1442. THE BELL SYSTEM TECHNICAL JOURNAL, SEPTEMBER 1981
i TECHNOLOGY

"The firs consideration in citent design ithe ehoice ofan intogeated
‘ieent trelnclogy. The choice of technology wil pet he Tllowing
sroas: the system performance in terms of spovd and power: the ct
‘ofthe devico whieh ielated to silicon aren or cieuit donaity; and the
ype of Tog Tunetions whies can be implemented by the specific

vehnslogy.
‘The N-channel wosrer (metal-orido semiconductor, fal. ffect
andlor) or NMOS lechnulogy enn easily implement. the following

logic functions: INVERT, NAND. NOR, XOR, XNOR. Flip-Flops.
Shift Registers; and compies logic OR-AND-INVERT, AND-ORIN-
VEICTho 40s technology, hy implementing these ciferen forms of
logic, can provide high funexional dersicy an compared toa technology
‘which eretricted to fewer forme of logic gatas.

‘The majority of ox eireuty isa aynchronous sytem wherein dara
are transfered betseon registers ec a. MHz ate, The citieal path i
10 logic gates deep: therefore, the technology must be capable of gate
‘lay of 20 ne oF lees (wore case) nt a power level compatible with
‘he sr level of intezration.

"The Aeplotionload wos tochnology wae selected for implementing
lho nse. Ths can existing process presenly used for manufeccoring
static memory devies.‘The exiseance ofa manufacarahle races has
the advantage of decreasing the design Lime and decreasing the risk of
developing a device. This technology provides the performance, speed
fal per, necranary for the DF reqiiement, a well ts allowing
high-density layout for implementing the 7900-71 equivalent gate of
logic, 2.5 KC bes of rain and 16 bits of kos

mm. ciRcurT LavouT
‘The final verultof circuit design iss layout daca bace used to make
aks, These tasks are used in wafer fabrieation to produce an
integrated cite. ‘Theee are diferent layout approaches oF sles 2
frome and compcct devices, These different acylen optimize either
Ceruit density ar design time and time to produce final integrated
‘sous, ‘The fin ple ie known as custom avant, where each device
ie crested kt connected with the runimm rstiens, Thu esr
luvout stv optimizes circuit density which reals in Ue fastest speed
tnd lowest power. The second ale is known at polyecl layout. This
layout ale uses established ols lie Ravel level whieh Tove
‘been designed, laid oul, und electrically verified. A eumpuler-sied
design (CAD! System own a5 11x" can automatically place and
‘oom Uno poled funetionsaceneing Lom logie desertion kon
‘e281? The nolvelllaynat ste prudices Une hotles me ilerval
from the scars ofthe cizcuit design stage Lo coupleton of an integreced
threat meeting the aysiu repre nis.

"The oe memories, Ratt wil ROM, constitute a large numbor of
tvanvistne ina regular pattern, For this reason, iin dearable couse 0
fustom layout aigle Gir msn co achieve the highese possible
‘ranaictor density and wore Une Inst amoone of slcon area,

‘The av performs «16 iy 20 51 wuliplicaion and «40-bit ccow
suulacion, along with oller functions. "These functions require logic
‘hich ia performed occa bile in yaale, rexating fn bit-onsented
Togie."Tassa portions hve Un functional lic veplicated up vo 40
times depending upon word length eepitod. Bxemplay of the logic
performed in the ati the 20-bc ad Funclion thal must he completed
‘riehin one lock eyele. This path and lle wile pat are up to 10
Togie gater rae, eling ithe eulromane that woret-cape rteal-
th gat delay uate es than 30s co fi within the 200 ns cycle
Consideration of the apaed requirements in the Att ond the regular
“haruteniscies of mach of the Jogi, lead (o Une choice of rast
Tayo sigle iw this section to optimize siren density. speed, and
power,

The 1040 seetion, which conkiste of the 1/0, at, al ental
actions, hin bath random and bit-orienced lovie. Cusiom layout was
selected for Un il-orented logic ro obtain the higher citeit deni.
"The toa radon logo a & gates deep and reals Ue requirement
Unt a woseeane gate delay mast be less Una 40 ws. Polyenl yout
ould nieet chia speed roquivemene nnd wis ehnsen for che vendor
Tage sections to decrease the design ine ofthe project. Polvells far
Uw epletinnload saws eechnology did nol exik whee Ue eit
design sage of the Osh was starr thenefore,polvcalls ware fet
Yiefined and ereated before the 1040 rari Toye sections could be
started.

‘Both eustom and pote! layout eves were used inthe Ds layout
CCartom layout wes dso in thr wenury end hicorganized seins to
fptimize circu density, seu, xv! power. Pelscall layout was ued in
the randem loge sertion minimize design tie, The resulting lsyouls
fave showa Unt the cust logie section achieved about tice che
functional density with afuclur of SiemimivemenLin ube speed achieved
tora given power level.

Iv, CARGUFT DesiGN PROCEDURES

Knowing che eype of logic functions that cn he implemenced wich
the sno technolo, the logic designer crapleted the logie deecrption
far the DS, The crit elestgner, having determined che layout sve,
Tied tn convert che logic nats wo K08Urnntors. Figure 2 shown hia
droit deign macedure. ‘The proposed. vrcuil is cuuvzed using

11444 THEBELL SYSTEM 'ECHNIGAL JOURNAL. SEPTEMBER 1081
St

a
wer Lt

circuit simulator such as sricx.* After a succesful simulation, the
SGreuit is converted to) mask levela an an in-bouse minicomputer
sraphics sytem. Physical layout design rules fr lines and spaces are
tse (0 ereaie geometries necessary for creating a mask for wafer
{ibrieation, Thore are two computer aide for verifying the layeus. The
Fit aid checks for violation of the physical Layout design roles. The
second nid determines the sie and lype of tramaitors and the parasitic
‘capneilanoe which ivan Impartant parameter for eveit performance,
‘This circuit characteriation representa a more accurate creat de
seripton than wae wuts simulated befor lavout, and these resulta
trust inthe eile shmlaor en decermine final veut performance
Tn mlcltion, computer plots ofthe eee layout ate visually checked.
for design rule layout errs fanelivel zrur, wl interconnect cor,

¥. CiRcUIT CONSIDERATION

‘The single mos! important factor which made He ceeuit deayn of
the Dar practical in thal the PsP ea synchranens yen whervin lala
flows between registers in a specified time interval This allows for
sireut simulations of rlacively smal seccions since che exact timing is
‘rll known,

‘Signals, whether they are instructions or data, ere parced. between
the major sections (au, Rast ROM, AAV. 1/0. CONTROL) via w 20-bit data
bus The 5-Mlz system clock hus two phases known asa master ond
slave phnee of 109 ro each, The data bs clarge during nese
hase und is discharged during the master phase by the sending port,
Iebe dat bit is ue

Synchronization becwesn the various secionsi achieved by distil
luting & master clock and a aynchyonization signal and neal regen
frsting the required clocks De-skevring networks were included in
tach section to achieve precise clock eynchronization even in the
presence of mascer clock delays due to resstance-cspactance loading
felay effete,

YLSIIMPLEMENTATION 1445
Power and ground hus distribution is imporiant to maintain aden
quate noize mira. Fach raajr section of the Ds bas its own power
nd ground to minimize che accumulation of voltage drops and noise
Inceractions due lo transients. The sie of hese Hines wis made lege
enough to keep wors-cie power and ground drops below 100 mv.

"The input and stp buffers ware located al the ege of che chip
and separate power and ground lines were also provide for these
‘sreuite, Both the peripheral placement of 1/0 buffers and provision
for their soperate power and ground busting minimize extemally
induced nose effects on internal logic.

‘nternal vesting probe pads were ditrbuted along the data bus, the
‘address os, and selected control and timing signal paths 20 tha the
[RO Hast, ROM, ad #946 old Be ested independent of each other for
‘agnostic testing and logic verifications. These ads di not increase

is. SD sgl proc intgatd cet

1440. THE RELL SYSTEM TECHNICAL JOURNAL, SEPTEMBER 1981
{he fn chip se and seminal in alying initial device testing
resull

Mi. CONCLUSIONS

‘The vratsiloon implementation of he nse haa heen described. The
nen intogented cieuit meets the system's requirements—funecion,
‘med an power, Figure 2 shows the chip, which containa 7200 rte
sivatent logic gates, 18K bite of nox, and 2.5 K bits of Rast. The
Implemencacion requires 45,000 transztors and ooeupies an anes of €2
smn GL by 86 ma

Vil ACKNOWLEDGMENTS

We sinceruy Unanke the muany_prople al Bell Talwrstares wha
concribuced to the development ofthe Ds In putiulue, we are very
fractal to Bailey Be, Jonos for hin efforts in wer falcata of the

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eRe EL ie Be hc, Pog ill Salat

Sephle e len ben Sgn kan et le,

YLSIIMPLEMENTATION. 1447