BSTJ 60: 7. September 1981: Accurate Logic Simulation Models for TTL Totempole and MOS Gates and Tristate Devices. (Levendel, Y.L.; Menon, P.R.; Miller, C.E.)

6.6 MB·English

Accurate Logic Simulation Models for TTL
‘Totempole and MOS Gates and Tristate
Devices

By Y.L. LEVENDEL, P. R. MENON, and ¢. E. MILLER
(Moruscritreslved Decomber 16, 1880)

The two logic values 01, and the unknown, are not sufficient for
caceuraiely simulating the behavior of rx. tatompote and Mos fates
and tristate devices, Furthermore, the classical fault modes (output
stuck and input open} are not sujfcient to eover the faulty behavior
Of wos devices. A previous soldion to the sizulation medeling re
(quired the addition of pseudo gotes, which have no physical meaning.
This poper develops methuds of mudeling fault jree and faulty tristate
devices for lnie simtlation. The morll ides rol reguire ary add
Fionad circuitry. bu the existence ofa simulator capabte of simulating
any nuenber of logic values is assumed

1. meTmopUCTION

‘A component Finding wide usage in the hasoriented urchiloebre of
today’s cempucersyannn i the estate driver. Atypical arrangement
ia shown in Fig Ln tis amangement there ate aeveral drivers, Only
‘one driver can be enabled ata time and “tak” oo the bus The receivers
capture the information on the bus

in Lensistor- transistor loge (01) technology, eriatate devices allow
‘us wiring, previously oblained only with convention open collector
‘oulat Tr, They also allow the wee of setive pull up to charge the
Tange capacitances associated with the hus. This leur, wold
rth conventional bus wiring technique, mess wy) the operation
tho bus In 0s tochnology, similar effects can be achieved with lover
power requirements, Here, we shall consider TH. toterpele, eos,
Pxc08 and NMOS bistate and trstatedeviees and show the similarities
and differences

In triste Lechnolosy, several malfunetions due to the presence of
faults or to.a wrong ullzation of the bus may eceur. Theso malfunc
‘tons may invalidate tesctemlts ar damage the components, Theretone,
{ts important to wimlate accurately the oporntion of faulty and flt-
rw crusts eontaining Buse, and other iste levees

has been shown thar the elasial fale modes (outpt tuck, iapot
‘open re nol aulcient to oover the faulty and faut-ree bebavior of
‘cmon deviog One attempt In heen made to map these full ffecls
Ineo elasieal seack-type falls by aliing cicuicry to the faull-free
‘dreut"Tieadaitonal eecoitey in ued to provide the faulty and full-
free ciraite with ‘mmory properties, which exist in cwos doviows
luler certain conditions. This muppicy allnwn the uae of a fault
situulator, which simulates only classen! fault, for simulating aul
‘og devioes. in fact, he limitations ofthe available eimolacor 92s
fematzaint on the propeted modeling. Although modeling ofthe ful
thee trntace doves leo used einilay add eieiry, Ne foe Tow,
sb over ur hs contenson which may damage the devices, was not
ovorod by this noel

hie paper develops methods of modeling fultree and fauley
trimate devices for loge simulation, without additional cicuitry. How
fever: it assumes the exience ofa simulator capable of stmulating any
‘umber of loge values. Both the memory properlion of Ds devices
dd the eer fs contention aze ahown Co be modell accurately
by the propoved mod

1.1 TTL tate tectmotoay

Consider the cistat invorter of Fig ix which A i the data input
sand Piste enable lead, The dove is enabled and acs as an invertor,
‘when = 0 as shown in Table L When. the invertor i disabled, i
semumes s high impedanoe, namely the impedance betwoen V, snl
Vand the impedance between Ve and Vo inextramely lange. Vor Veo.
and Ve are che ontpnt, mpply and ground volages roppectively

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“Table |—Truth table for tristate ete

ae

"The 177 lristae inverter can be modeled as the connection of to
funetions 7, and 7, (Fig. 3} which are controlled by lines A and E.
andl 7, can be either conducting (on) or nonconducting off) and they
‘operate according to Table TI, The device iin the high-impedance
tata when both T; and 7; aro off Tn a tistace bus system, several
‘ietate deviogs are oird logeter and he ayer operates ately fat
Thm evi wna acne tae (Fig 1).

‘Two problema have emerged in Lists lochrology ana they ate
seeoriated withthe trvcture of the rsa device The Rie dienlty
‘concerns a disabled trstate device and its abilicy to source or sink
‘ourvant depending on the value of te output voltage. These re eases
te lustre in Pig 4. One en iencty a voltage Va, auc that. if V,
> Vn, then 7, act aga current sures, and if Va < Vin 7. acts 8
Siok "Theshold valeage Va in 2 voltage between Vee and Vo, whichis
“devermined by the outpuc properties ofthe device

“able Truth table for irverter model

Ia receiver is pret on & bute, ie connected to Vi—the

diver wil source or sink current and, as a rebut, the output Vo may
reach the input threshold voltage Vix ofthe receiver. The output of 2

Losi smuLaTION MopELS 1273,
|] ots

Py 4 Dinah af} Se) Sears

receiver withthe input volage equal ta Vai unknown and in fact the
tutpat may aseilae due to savall variations around Vn. Normally,
titer all the driving devices heenme disabled, the existence of the
leakage current fz il Uesiroy Une previo logic value of hus and
‘he bus wil “oat.”

‘acoond penblom occurs when a last two tistate device feeding
‘abusave simultaneously enabled and arein opposite activo logic states
(Wig. 5) Under this condition, tho bus voltage may be anywhere in the
range becwoen the aoliveIogielvele und the cargunts may become
‘extremely large (Pig. 6b). Tho actual value of Ve and Z- canbe

Ay of

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Aetcrminod fom che current-voleage characterise of tho tw doves,
‘This condkion, called overlsp, may cause excessive device hosting
resulting in device failane or alomly degrade the dovice, causing a
decrease i ie

‘Tn simulation, ts important vo corretly model the effocts ofthese
toro problems, so thats mulation user ean be warnod ofthe existence
fof potential diffutten For instance, primary inpul-ouipt. bis
should be disabled (losting) before a test can bo upplied to it and
‘enabled before the result of test can be read from it. Also, anincorrect
‘evign or toot sequent may eae overlaps on buses andthe simulation
should produoe 4 warning

1 TTL TOTEMPOLE, CMOS GATES, AND TRISTATE TRANSMISSION
Devices

2.1 Putup and puttiown functions

Consider the enos and 1 implementations of an inverter (Fg. 6).
‘They have n common structure, which can be generalized by the
diagram of Fig, for multiple ippur gates. Tis structure is composed
of a pullup function (ror, a pulldown fonction (eDF}, and an inte
trator F)."The Py and vor depend upon the input wate = 9
fi the integrator produces the output ¥ depending upon Ya od Yon
[Alo the Fur and the ror are complementary and cennot produce the

LOGIC SIMULATION MODELS 1275
ame logic value under normal circumstances, By convention, Ys ot
Yo has the value 1(0), when the wor or the vor is on(of). The
Inlegrtor Z haa the behavior of Table TH, except in the case of
rmalfunetions, Aa an example, consider the cwos, NAND gata of FR. 8
‘The janetions P, and P, realize a Nano function, whereas N, and Ni

realize 4 AND funetion

Table Il—Truth table tor

“Integrator
72 Tayette
H tite

22 Tiatate devices

‘A goneral tos oF Tr tristate devioe ean be modeled asin Fig. 8
"The symbol E represents an enable Tine aul both PUF and PDF can be
simultaneously disabled. Under normal conditions, the PUY and ror
cannot be simultaneously active, The integrator Tis dseribed in Table
Vv

Table V—Truth table fr tritate

inane
a
Pot Be

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Unually,tristate vies are usod in the mode shown in Fig. 10. In
she illustration, E., Fy, «+ Ey see the enbling lines. There are several
‘intersting cases, namely

Ui) all he deviees are dieabled,

id) One deveois enable.
(ui) Two o more devices axe enabled with opposite logic values.
‘These three cases lee to differen npedanee situations on the Duss
and hey are represcnted in Table V. Inthe context of simulation, iis
powible to find a fourth situation, when the impedances are not known,
‘This can be ent by nn nknown value on the enable Hine F of
device,

>
Ui
—| I

Loic SMULATION WODELS. 1277
‘able V—Devion states and bus impedances

a ee
= aoe
ot er

2.3 CMOS aynamte proper

‘The main difference between cMos and rr. cidtatadavices is that
the Inakage currents in ekos azo extremely emall compared to WL,
leakage currents, Input currents for Mos are alo scl. Therefore if
sexs devices fist enabled and then disabled, the small capacitances
tn th bus wil remain charged fora long period of tie and the bus
vill appear to receivers ait were remaining at the same loge value.
Uieimately, the capacitance will be discharged, but if the rate of
‘operation is sufficiently fast, Uno discharge time can be considered as
infinice and the bas displays memory properties. However, if foreed to
tn active logic valuo, the bus will immediately reach this value inde-
pendent of this charged eapacitanos. Th 37. tristate devices, the
leakage ourenta bing lange, the dncharge cine becomes nal and no
memory i displayed.

2.4 Logle values and impedance

It should be clear from our preceding discussion that sccurate
simulation modeling of tristate devies requires two ditinet concepts:
logie vahie and impedance. Three logic values, 0,1, and u, are widely
tsed in emulation, the symbol u being used to represent unkown,
signal values Trinown signal values may be present because the
‘nitial values of some leads may he unknown or because of races ot

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‘ouillatons. The effects of impedance on circuit behavior depends on
the technology, For instance, a high impedance may appear as an
‘unknown logs value in 7. tristate technology. On the other hand, an
‘utp whic has high impedance in cos technology wil remember
the loge value before the gate was disabled, Simiary, a conflict on a
bus may appear ae 0,1, oF u depending om the Uschnolegy

‘During simulation of ceite containing tritate device, i impore
lant tobe able to detect special situations ike bus confit, Tests that
‘auge bus conflicts may resut in damage tothe devices and must be
‘voided. Inthe Uster environment, che state of an output bus in the
high-impedance sinle may be altered by the tester, invalidating the
test Those considerations lead to the representation of the state of «
line by a pair eomposed af che impedance value and che logic value.
‘There will be four porsible impedance values (Table VI). Therefore,
we obrain 12 combinations of impedance and logic value (Table VI.

peat
tepstane MS
Rete Hi
tim t

Tt kage —
hte wit a nw inpedance
AS Hee Ent i ete te menor

HR dake ran noon pcan tle memary

“These 12 logic combinations, which we thal cal Tog values in the
‘conter of simulation, zeprevent a delaled unalysis of triste devices
tid any one of these correspon to a posse situation. Two cases
are lstrated in Fig. 11 wl both eaten display memory properties. In
‘the fret case Pig in), the enuble line yoes from 00 wand the output
ives from F/0 10 1/0 (unkown impedance). Inthe second case (Fi
1b), the erable Tne gow to 1 and the impedance goea trom H to H,
‘with the sume logic value,

LOGIC SMULATION MODELS. 1279
Re 11Detamnain af npean

1 i ponsble to reduce the number of values in ‘Table Vil at the
expense of some information. ‘The result is Table VILL, which ahows
two possible sets of loge values for Tr trstate devices. Z and a are
synonyms for the puis H/u and C/a, respectively In ot 2 paired and
‘Dore differentiated, Pair 12 called a potential confit (a") and ean
‘eur in various situations (Fg. 12). In this case, the simulation will
declare a potential bus overlap. In set 1, pais d and 12 are not
Aliferentiaved and some information may be lor. In vv. cochclgy,
‘he unused combintions correspond to impossible situaions (ed, Dale
10) oF to unpredictable situations tex. pur

“Table Vil—Two sets of logic values for

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