Audio power amplifier techniques with energy efficient power conversion. Vol. 2

209 Pages·2017·10.21 MB·English

by  Nielsen, Karsten

Audio Power Amplifier Techniques
With
Energy Efficient Power Conversion
Volume II
Appendices
Ph D. Thesis
Karsten Nielsen
Department of Applied Electronics, Building 451
Technical University of Denmark
DK-2800 Lyngby
April 30,1998
DISCLAIMER
Portions of this document may be illegible
in electronic image products. Images are
produced from the best available original
document.
Appendix A - Contents
A. 1. Efficiency for various amplifier classes...................................................................A.2
A.2. Class B..........................................................................................................................A.2
A.2.1. Realistic Class B model........................................................................................A. 3
A.2.2. Class B2..................................................................................................................A.4
A.2.3. Class BX.................................................................................................................A.5
A.3. Class G..........................................................................................................................A.5
Appendix B - Contents
B.l Double Fourier Series development for PWM...........................................................B.2
B.2 DFS expressions for fundamental NPWM schemes..................................................B.5
B.2.1 Natural sampling - AD - Single sided (NADS)................................................B.5
B.2.2 Natural sampled - BD - Single sided modulation (NBDS)...............................B.6
B.2.3 Natural sampled - AD - Double sided modulation (NADD)............................B.9
B.2.4 Natural sampled - BD - Double sided modulation (NBDD)..........................B. 10
B.3 Double Fourier Series development for PSCPWM.................................................B.12
B.3.1 DFS synthesis for NS PSCPWM......................................................................B. 12
B.3.2 DFS synthesis for ND PSCPWM......................................................................B.15
B.4 DFS synthesis for BNS1 PSCPWM...........................................................................B.18
B.4.1 DFS for BNS 1 differential output.....................................................................B.20
B .4.2 DFS for BNS 1 commonmode output................................................................B .22
B.5 DFS for BND1 PSCPWM...........................................................................................B.23
B.5.1 DFS for BND1 differential output....................................................................B.26
B.5.2 DFS for BND1 commonmode output...............................................................B.27
B.6 DFS synthesis for BNS2 PSCPWM...........................................................................B.29
B.6.1 DFS for BNS2 differential output.....................................................................B.31
B.6.2 DFS for BNS2 commonmode output................................................................B.33
B.7 DFS synthesis for BND2 PSCPWM..........................................................................B.36
B.7.1 DFS for BND2 differential output....................................................................B.38
B.7.2 DFS for BND2 commonmode output...............................................................B.40
B.8 DFS synthesis for BNS3 PSCPWM...........................................................................B.44
B.8.1 DFS for BNS3 differential output.....................................................................B.46
B.8.2 DFS for BNS3 commonmode output................................................................B.46
B.9 DFS synthesis for BND3 PSCPWM..........................................................................6.48
B.9.1 DFS for BND3 differential output....................................................................B.50
B.9.2 DFS for BND3 commonmode output...............................................................B.51
B.10 DFS derivation for uniform sampling...................................................................B.51
B.10.1 Uniform sampled - AD - Single sided modulation (UADS)..........................B.52
B.10.2 Uniform sampled - AD - Single sided modulation (UBDS)..........................B.53
B.10.3 Uniform sampled - AD - Double sided modulation (UADD)........................B.54
B.10.4 Uniform sampled - BD - Double sided modulation (UBDD)........................B.55
Appendix C - Contents
C.l Nielsen, Karsten
"High Fidelity PWM based Amplifier Concept for active speaker systems with a
very Low Energy Consumption"
100th AES Convention. Copenhagen, May 1996. Preprint 4259.
C.2 Anderskouv, Niels, Nielsen, Karsten, Andersen, Michael
"High Fidelity Pulse Width Modulation Amplifiers based on Novel Double Loop
Feedback Techniques"
100th AES Convention. Copenhagen, May 1996. Preprint 4258.
C.3 Nielsen, Karsten
" A Review and Comparison of Pulse Width Modulation methods for analog and
digital input switching power amplifier systems "
102nd AES Convention. Munich, March 1997. Preprint 4446.
C.4 Nielsen, Karsten
" Parallel Phase Shifted Carrier Pulse Width Modulation (PSCPWM) -
A novel approach to switching power amplifier design "
102nd AES Convention. Munich, March 1997. Preprint 4447.
C.5 Anderskouv, Niels, Nielsen, Karsten, Andersen, Michael
" Single Phase Low Distortion DC/AC Inverter With High Bandwidth To
Switching Frequency Ratio "
EPE 97. Trondheim, Norway. 8-10 September 1997. pp. 2214-2219.
C.6 Nielsen, Karsten
" High Fidelity PWM based Amplifier Concept for active speaker systems with
a very Low Energy Consumption "
Journal of the Audio Engineering Society. July/August 1997. pp. 554-570.
C.7 Nielsen, Karsten
" Pulse Edge Delay Error Correction (PEDEC) - A Novel Power Stage Error
Correction Principle for Power Digital - Analog Conversion”
103rd AES Convention. New York, September 1997.
Preprint 4602 (47 pages).
C.8 Nielsen, Karsten, Taul, Thomas, Andersen, Michael
" A Comparison of Linear and Non-Linear Control Methods for Power Stage Error
Correction in Switching Power Amplifiers “
104th Convention of the AES. Amsterdam, Holland. May 1998.
C.9 Nielsen, Karsten
" PEDEC - A Novel Pulse Referenced Control Method for High Quality
Digital PWM Switching Power Amplification "
IEEE Power Electronics Specialist Conference (PESC). Japan, May 1998.
Appendix A A. 1
Appendix A
Contents
A. 1. Efficiency for various amplifier classes.....................................................................2
A.2. Class B............................................................................................................................2
A.2.1. Realistic Class B model.............................................................................................3
A.2.2. Class B2.......................................................................................................................4
A.2.3. Class BX.......................................................................................................................5
A.3. Class G............................................................................................................................5
A.2 Appendix A
A.l. Efficiency for various amplifier classes
In the following, the power and energy efficiency is investigated for three widely used
analog power amplifier methods. Analytical expression for the ideal efficiency are derived
and subsequently compared. Following, more realistic models are investigated. First, some
important parameters used throughout the following are introduced. Let x denote the
relative output level. The amplifier output power is then:
PlM = xlWL (A.1)
The power efficiency is the ratio of utilized power over the supplied power:
Pjfxf
tj(x) =
Ps(x) (A.2)
The energy efficiency is defined as the ratio of used energy over the supplied energy over
time. This requires knowledge of how the amplifier is used. Consider a set of date for the
amplifier use and power dissipation:
(nl > Pq,\ ’ ^£>,1)’ (n2 ’ Pq,2 ’ ^£>,2 )> •" (ft-N’Po.N ’Pd,n) (A.3)
where (nJ,P0 j,PDJ) refers to that the output power in average is p0 j in nj percent of the
time, and PD j refers to the losses at the given output power. The effective output power
and the effective power dissipation are. The energy efficiency is derived directly from these
data as:
Sn-'V,
! L,E L,E
(A.4)
P n i D JV N
SI “ Z", fzu+Z", P.,
/=!
77E represents the real amplifier energy efficiency, i.e. TjE is directly indicates how much of
the supplied energy, that is utilized in the speakers.
A.2. Class B
Fig. A.l shows the simple Class B output stage topology. The output devices are only
active during half of the signal cycle. Fig. A.l (right) shows the output voltage and the
supply rail voltage, that determines the voltage drop over the active output device. The
supplied power can be found as a function of x by integration over a period of the signal:
1 r xV 2V2
Ps,B(x) = 2—jV—sin(QX)d((Ot) = x^- (A.5)
The efficiency can now be derived:
Appendix A A.3
■=F V
Fig. A.l Class B amplifier (left) and essential signals (right).
, . 2 Rl n
nAx)=~^~=xi, (A.6)
kR,
Another interesting parameter to consider is the power dissipation which is used in heat
sink design considerations. The total power dissipation is:
Pd (*) - Pc(x)~ Pl W -—(----~) (A.7)
RL x 4
Or relative to the maximal output power:
Pdn (-*•)'
(A.8)
PL, maxO) 2 K
The ideal power amplifier thus has a maximal power dissipation of:
PD,max = 0.4PL „
(A.9)
A.2.1. Realistic Class B model
It has been assumed above, that the class B amplifier was ideal. However, a practical class
B amplifier will either implement zero quiescent losses or a 78% efficiency. If two factors
are added a more realistic model arrives.
• Quiescent losses. This is caused by the inevitable bias current that are necessary to
linearize the output stage [Be88].). The is also called Class AB since the angle of
operation in each transistor is now more than 180 degrees.
• A finite headroom. The output transistors have a saturation voltage and general
amplifiers will clip at 85%-90% of the supply as opposed to 100% for the ideal
amplifier. This
With these two simple modifications the resulting model is remarkably accurate.
A.4 Appendix A
■=p (l-a)V
■=f (l-a)V
Fig. A.2 Class B amplifier (left) and essential signals (right).
A.2.2. Class B2
A simple improvement of the classical class B amplifier topology is shown Fig. A.2. By
using four power supply rails considerable improvements in overall efficiency can be
obtained. When the output signal is lower than aV, all current is delivered from the lower
supply rails, i.e. the power dissipation in the bottom transistors are reduced. Since the top
transistors are not conducting at all in this situation the overall efficiency is improved over
class B. Although Class B2 is topologically simple, the implementation is complicated by
the requirement for four power rails which increases the complexity of the power supply.
The total supplied power is now the sum of two contributions:
2 7:
x------a (x<a)
(A. 10)
n
2 V2
x—K R—l “ + (1-a)LAsin(ax)d(ax) (x>a)
The two partial expressions:
2 V
PS1,B2(*<°0 = (A.ll)
1t kl
2 y- /—
PSiBi(x,a) = x-—(l-a) 2 sin(oyt)d(ax)
(A. 12)
nIT. RK. V/'vaSisnifn—(-))
x
Represent the contributions from the dual supplies ±aV and ±V respectively. The
efficiency as a function of relative output level can now be written as:
Appendix A A. 5
Fig. A.3 Class B amplifier (left) and essential signals (right).
y- (;«%)
4 a
(A.13)
7]B2(x,a) = - n (jc>a)
(z,«)
5,82
a + (l-a)\2 sm(cot)d(ax)
JasinC—)
The integral contains integration limits that makes it complicated to solve. Instead,
numerical methods is use to investigate the expression below. The normalized power
dissipation for class B2 is:
2x x2 .
—cc-----(x < cc)
(x,a) n 2
(x,a) = D,B 2 (A.14)
‘ DN,B2
Pl, 2x-a a + (l-a)f* a sin(<Br)d(fi») x (x>a)
7t Jasin(-) ~2
The voltage division factor a can be used to optimized the amplifier energy efficiency.
A.2.3. Class BX
Class B2 could be extended to Class BX with 2X power rails total. However, practical
implementation issues puts strong limitations on such extensions, and 6 levels total (3
positive and negative) is thus considered the maximum.
A.3. Class G
Another possible amplifier topology can be realized by a more intelligent control of the
power supply voltage. If the positive and negative supply levels are both controlled by a
DC-AC inverter, the rails can be controlled such that the voltage drop over the output
transistors is dropped. Note, that the power supplies are now effectively amplifiers
generating an AC output form a rectified DC input, controlled from an AC input source.
The bandwidth requirements for the power supply are the same as for the amplifier. One
might argue that the system consists of three amplifiers i.e. the topology is complex. Only
the linearity and noise requirements for the switching power supplies are not necessarily as
high as for the amplifier, since power supply rejection ratio can be provided by feedback.
A.6 Appendix A
The total supplied power from the power supplies is found as the sum of the equal
contributions from the positive and negative power supply:
T •
_ 2 r* xV
-sin(cof)[xV' sin(mt) + fiV\l(ox)
2k Jo Rl
(A.15)
]xV
£ x sin2 (<ut) + /? sin(<Hf )c? (cot)
K Rl
V2 f+2f)
=XT,{
Where it is assumed that the power rail voltage is the load voltage plus the factor ft V. The
efficiency can now be derived:
PlW 1 (A. 16)
X-(- )
4 P+x*
Obviously, the efficiency increases as the voltage headroom factor ft is reduced.