Asynchronous System-on-Chip Interconnect

150 Pages·2002·4.168 MB·English

by  Dr John Bainbridge (auth.)

Distinguished Dissertations
Springer-Verlag Berlin Beideiberg GmbH
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Jo hn Bainbridge
Asynchronous
System-on-Chip
lnterconnect
Springer
Dr John Bainbridge
Department of Computer Science, University of Manchester, Manchester M13 9PL
Series Editor
Professor C.J. van Rijsbergen
Department of Computing Science, University of Glasgow, G 12 8RZ, UK
British Library Cataloguing in Publication Data
Bainbridge, John
Asynchronous system-on-chip interconnect. -(Distinguished
dissertations)
l.Asynchronous circuits 2.Integrated circuits
3.Microcomputers -Buses
I.Title
621.3'815
ISBN 978-1-4471-1112-2
Library of Congress Cataloging-in-Publication Data
A catalog record for this book is availab1e from the Library of Congress.
Apart from any fair dealing for the purposes of research or private study, or criticism or review, as
permitted under the Copyright, Designs and Patents Act 1988, this publication may only be reproduced,
stored or transmitted, in any form or by any means, with the prior permission in writing of the publishers,
or in the case of reprographic reproduction in accordance with the terms of licences issued by the
Copyright Licensing Agency. Enquiries concerning reproduction outside those terms should be sent to
the publishers.
Distinguished Dissertations ISBN 978-1-4471-1112-2
ISBN 978-1-4471-1112-2 ISBN 978-1-4471-0189-5 (eBook)
DOI 10.1007/978-1-4471-0189-5
a member ofBertelsmannSpringer Science+Business Media GmbH
http://www.springer.co.uk
© John Hainbridge 2002
Originaly published by Springer-Verlag London Berlin Heidelberg 2002
Softcover reprint of the hardcover 1st edition 2002
The use of registered names, trademarks etc. in this publication does not imply, even in the absence of a
specific statement, that such names are exempt from the relevant laws and regulations and therefore free
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Preface
A shared system bus is a key feature of modern system-on-chip design methodologies.
lt allows the independent development of major macrocells which are then brought
together in the final stages of development. The use of a synchronous bus in a
synchronous design brings with it problems as a result of clock-skew across the chip
and the use of many timing domains in a system. In an asynchronous system, the use
of a synchronous bus would subvert many of the benefits offered by asynchronous
logic such as reduced electromagnetic emissions.
This book was written as a doctoral thesis submitted in March 2000. lt describes
an asynchronous system-on-chip bus which offers a solution to such problems.
Existing shared-bus techniques are re-investigated in the context of an asynchronous
implementation, and a complete bus design is presented that was developed for use in
an asynchronous subsystem of a mixed-synchrony chip. This chip was to form part of
one of the first commercially available products to incorporate components that used
asynchronous very large scale integration (VLSI) techniques, but was never
productised.
The split-transfer primitive, often avoided or added as an optional extension by
synchronous designers, is used as the basis for the chosen bus architecture. lt offers a
fine-grained interleaving of bus activity and a better bus availability than would an
interlocked-transfer technique as found in many synchronous alternatives. This
technique is viable in an asynchronous design because of the very low arbitration
latency.
Simulation results (and fabricated prototype chips) show that the proposed
architecture achieves a performance comparable with synchronous buses that use
similar levels of resource, whilst maintaining the benefits of the asynchronous design
style.
Since writing this thesis, work on asynchronous logic has been ongoing, and some
of my suggestions for "future work" are being explored [7]. Further developments in
Asynchronous System-on-Chip Interconnect and asynchronous logic design can be
found online at our group World Wide Web pages which are permanently up to date:
http://www.cs.man.ac.uk/amulet
John Hainbridge
University of Manchester, UK
December 2001
Acknowledgements
Whilst working as a part of the AMULET group at the University of Manchester' s
Computer Science Department I have received support and inspiration from many of
my colleagues, especially those involved directly with the AMULET3 project. Special
thanks are due to a few individuals:
First and foremost of these is my supervisor, Prof. Steve Furber without whose
valuable guidance and support this work would not have been possible. Many thanks
Steve.
Dr Jim Garside and Dr Steve Temple have provided much advice on low level
implementation issues and assistance with the CAD tools when problems arose,
including a hack for the y2k bug of the Compass Design Tools. Steve also served as
an interface to the commercial partners of the project, proof-read the book and
manually laid out the top-level wiring of the chip.
Dr David Lloyd performed the unenviable task of converting my behavioural
models written in an in-house language into a VHDL model for use by our comrnercial
partner, and in the process raised many interesting issues for discussion.
Finally, I would like to acknowledge Dr Andrew Bardsley, Dr Phil Endecott and
Dr Dave Gilbert for many useful discussions; Dr Doug Edwards and Prof. Ian Watson
for introducing me to the fine arts of navigation and the downhill ride to the pub; and
my parents for their timeless support whatever I choose to do.
Contents
1. Introduction ......................................................................................................... !
1.1 Asynchronous design and its advantages ................................................... 2
1.1.1 Avoidance of clock-skew ............................................................... 2
1.1.2 Low power ...................................................................................... 2
1.1.3 Improved electro-magnetic compatibility (EMC) .......................... 3
1.1.4 Modularity ...................................................................................... 3
1.1.5 Better than worst-case performance .............................................. .4
1.2 Disadvantages of asynchronous design ..................................................... .4
1.2.1 Complexity ..................................................................................... 4
1.2.2 Deadlock ......................................................................................... 4
1.2.3 Verification ..................................................................................... 5
1.2.4 Testability ....................................................................................... 5
1.2.5 "It' s not synchronous" .................................................................... 5
1.3 Book overview ............................................................................................ 5
1.4 Publications ................................................................................................ 7
2. Asyncbronous Design .......................................................................................... 9
2.1 Introduction ................................................................................................ 9
2.2 Asynchronous design ................................................................................ 10
2.2.1 Circuit classification ..................................................................... 11
2.2.2 The channel .................................................................................. 11
2.2.3 SignaHing conventions ................................................................. 12
2.2.4 Data representation ....................................................................... 13
2.2.5 The Muller C-element .................................................................. 15
2.2.6 Specifications and automated circuit synthesis ............................ 16
2.2.7 Metastability, arbitration and Synchronisation ............................. 17
2.2.8 Sutherland' s micropipelines ......................................................... 18
2.2.9 Large asynchronous circuits ......................................................... 20
2.3 Summary ................................................................................................... 21
3. System Level Interconnect Principles .............................................................. 23
3.1 Point-to-point communication paths ........................................................ 23
3.2 Multipoint interconnect topology ............................................................. 23
3.2.1 Shared buses ................................................................................. 23
3.2.2 Star and ring networks .................................................................. 24
3.2.3 Meshes .......................................................................................... 24
3.3 Bus protocol issues ................................................................................... 24
3.3.1 Serial operation ............................................................................. 24
3.3.2 Multiplexed address/data lines ..................................................... 25
3.3.3 Separate address and data lines .................................................... 25
3.3.4 Arbitration .................................................................................... 26
X Contents
3.3.5 Atomic sequences ......................................................................... 26
3.3.6 Bursts ............................................................................................ 27
3.3.7 Interlocked or decoupled transfers ............................................... 27
3.3.8 Split transactions .......................................................................... 27
3.4 Interconnect performance objectives ........................................................ 27
3.5 Commercial on-chip buses ....................................................................... 28
3.5.1 Peripheral lnterconnect Bus (PI-Bus) ........................................... 28
3.5.2 Advanced Microcontroller Bus Architecture (AMBA) ................ 28
3.5.3 CoreConnect ................................................................................. 29
3.6 Summary ................................................................................................... 30
4. The Physical (Wire) Layer ................................................................................ 31
4.1 Wire theory ............................................................................................... 31
4.2 Electrical and physical characteristics ...................................................... 32
4.3 Termination .............................................................................................. 33
4.4 Crosstalk ................................................................................................... 33
. 4.4.1 Propagation delay for well separated wires .................................. 35
4.4.2 Signalpropagation delay with close-packed wires ...................... 36
4.4.3 Alternative wiring arrangements .................................................. 36
4.5 Summary ................................................................................................... 40
5. The Link Layer .................................................................................................. 41
5.1 Centralised vs distributed interfaces ........................................................ .41
5.2 SignaHing convention ............................................................................... 42
5.3 Data encoding ........................................................................................... 43
5.4 Handshake sources ................................................................................... 43
5.5 Bidirectional data transfer ....................................................................... .44
5.6 Multipleinitiators on one channel ........................................................... .45
5.6.1 Arbitration .................................................................................... 45
5.6.2 Request drive and hand-over ........................................................ 50
5.6.3 Push data drive and hand-over ..................................................... 50
5.6.4 Transfer deferral/hardware retry .................................................. 51
5.6.5 Atomic transfers and locking ....................................................... 52
5.7 Multipletargets ......................................................................................... 54
5.7.1 Acknowledge drive and hand-over ............................................... 54
5.7.2 Target selection ............................................................................ 55
5.7.3 Decode and target exceptions ....................................................... 55
5.7.4 Pull data drive and hand-over ....................................................... 56
5.7.5 Defer ............................................................................................. 56
5.8 Multipoint bus-channel interfaces ............................................................ 56
5.9 MARBLE's link layer channels ............................................................... 58
5.10 Summary ................................................................................................. 59
6. Protocol Layer .................................................................................................... 61
6.1 Transfer phases ......................................................................................... 61
6.1.1 Command phase ........................................................................... 62
6.1.2 Acknowledge phase ...................................................................... 62
Contents xi
601.3 Data phase 00 00 00 000 0000 0000000000 000 00 000 00 000 00 000000 000 0000 0000000000 000000 00 00000 00 000 00 000 62
6o1.4 Response phase 00 00 000 00 000 00 000000 00 00 000 00000 00 00 00 00 00000 00000 00 000 000 000000000000 00 0000 06 3
602 Exceptions oo 00 Ooo oo 00 0000 00 00000 00 00 0 oo 0000 000 0 00 000 00 000 00 000 000 000 00 00 000 00 00000 000 000 00 00 000 00 ooo 00 00 Oo 63
6.3 Defer and bridging 00000 000000000000 00000000 00 00000000 0000 000000 00 00000 00000000 000 00 000 00000 00 000000000 63
6.4 Mapping transfer phases onto channel cycles 000 0 0000000 Oo 000 000 00 000 00000 00 0000000 0000 64
6.401 Sequential operation using a single channel 00000000 00 000 000 00 00 000 000 00 00 00 06 5
6.402 Parallel operation using multiple channels 000 00000 00 000 000 000 00 00 000 oo 00 0000 06 6
605 Transfer cycle routing 000 0 00 00 000 00 000 000 00 000 00 00 000 00000 0000 00 00 00 000 ooo 00 000 000 00 ooooo 00 ooo 00 00 00 06 6
60501 Interlocked protocols ooooooooooooooooooooooooooooooooooooooooooooooooooooOOooooOOoooooooo67
6o5o2 Decoupled protocols oooooooooooOOOooooOOOoooooOOooooooooooooooooooooooooooooooooooooooooo68
606 Transfer cycle initiation 00000 00 000 00 000 0000000000 000000000000000000 00 00000000000000 0000000 0000000000 69
607 MARBLE's dual-channel bus architecture oooooooooooooooooooooOOOOooOOOOOooOOOOooooOOOo 70
7. Transaction Layer ............................................................................................. 71
7 01 Split transactions 000 00 00 00 00 00 000 00 000 00 00000 000 0000000000 00 00 00 00 00 000 00000 00 000000 0000000000 00 00 0000 07 2
7 01.1 Split transactions give better bus availability 00 00 000 000 000 00 ooo 00 ooooooo 00 oo 72
7 ol.2 Implementation on an interlocked protocollayer 000000 00000 00 000 00 0000000 72
701.3 Implementation on a decoupled protocol-layer 0000000000000000000000000000 74
7 02 Response ordering 00 0 0 0 0 0 00 0 00 0 0 0 0 00 0 00 0 0 0 00 0 00 0 0 0 00 0 0 0 0 0 0 0 00 0 0 00 0 0 0 0 0 00 0 00 0 0 0 00 0 00 0 0 0 0 0 0 0 00 0 00 0 0 0 0 0 0 0 7 4
70201 Single outstanding command oooooooooooooooooooooooooooooooooooooooooooOOOOoooOOOOo 76
7 o2.2 Multiple outstanding commands and pipelining 0000 Ooo 00 00 Ooo 00000 00 00 00 07 7
7 02.3 Nurober of outstanding commands 00 00 00 00 00 000 00000 00 000 000 00 000 00 000 00 0000000 00 78
702.4 A grouping of single outstanding command interfaces 0000000000000000 78
702.5 Sequence tagging and reordering ofresponses oooooooooooooooooooooooooooo 79
7.3 MARBLE' s transaction layer ooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo 81
8. MARBLE: A Dual-Channel Split Transfer Bus ............................................. 83
801 MARBLE protocol and signal summary oooooooooooooooooooooooooooooooooooooooooooooooooo 83
80101 Two channels 00 00 00 00000 00 000 000 00 00 000 0000000 000 00 0000 00 00000 000 00 000 00 000 000 00 00 000 00 0000 00 8 3
801.2 Split transactions 00000000000000000000000000000000000000000000000000000000000000000000000000 85
80103 Exceptions oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo86
8o1.4 Arbitration oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo 86
801.5 Atomic transactions and locking oooooooooooooooooooooooooooooooooooooooooooooooooo 86
80106 Burst optimisation ooOOooooooooooooooooooooooooooooooooooooooOOooooooooooooooooooOOoooooooo 86
802 Bus transaction interface implementation oooooooooooooooooooooooooooooooooooooooooooooooo 87
80201 Interface structure 000000000000000000000000000000000000000000000000000000000000000000000000088
80202 Data storage and manipulation 00000000000000000000000000000000000000000000000000000 88
802.3 Token management 0000000000000000000000000000000000000000000000000000000000000000000000 91
8.3 MARBLE in the AMULET3H system 00000000000000000000000000000000000000000000000000000 91
8o3o1 AMULET3 processor core 00000000000000000000000000000000000000000000000000000000000 92
80302 RAM ooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo94
8.3.3 ROM ooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo 94
8.3.4 DMA controller oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo 95
80305 Extemal memory/test interface oooooooooooooooooooooooooooooooooooooooooooooooooooo 95
80306 ADC/AEDL oooooOOooooooooooooooooooOOooooooooooooooooooooooooooooooooooooooooooooooooooooooo95
8.307 SOCB ooooooooOOOooooOOoooooOOoooooOOoooOOOoooOOOOoooooooooooooooooooooooooooooooooooooooooooooooo 95