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Asynchronous On-Chip Networks and Fault-Tolerant Techniques Taylor & Francis Taylor & Francis Group http://taylorandfrancis.com Asynchronous On-Chip Networks and Fault-Tolerant Techniques Wei Song and Guangda Zhang First edition published 2022 by CRC Press 6000 Broken Sound Parkway NW, Suite 300, Boca Raton, FL 33487-2742 and by CRC Press 4 Park Square, Milton Park, Abingdon, Oxon, OX14 4RN CRC Press is an imprint of Taylor & Francis Group, LLC © 2022 Wei Song and Guangda Zhang Reasonable efforts have been made to publish reliable data and information, but the author and publisher cannot assume responsibility for the validity of all materials or the consequences of their use. The authors and publishers have attempted to trace the copyright holders of all material reproduced in this publication and apologize to copyright holders if permission to publish in this form has not been obtained. If any copyright material has not been acknowledged please write and let us know so we may rectify in any future reprint. Except as permitted under U.S. Copyright Law, no part of this book may be reprinted, reproduced, transmitted, or utilized in any form by any electronic, mechanical, or other means, now known or hereafter invented, including photocopying, microfilming, and recording, or in any information storage or retrieval system, without written permission from the publishers. For permission to photocopy or use material electronically from this work, access www. copyright.com or contact the Copyright Clearance Center, Inc. (CCC), 222 Rosewood Drive, Danvers, MA 01923, 978-750-8400. For works that are not available on CCC please contact [email protected] Trademark notice: Product or corporate names may be trademarks or registered trademarks and are used only for identification and explanation without intent to infringe. ISBN: 978-1-032-25575-0 (hbk) ISBN: 978-1-032-25741-9 (pbk) ISBN: 978-1-003-28478-9 (ebk) DOI: 10.1201/9781003284789 Typeset in Latin Modern by KnowledgeWorks Global Ltd. To Chunzhen and Chao for their patience and love. To Mingyi and Jersey for bringing joy into our life. Taylor & Francis Taylor & Francis Group http://taylorandfrancis.com Contents Preface xv Chapter 1(cid:4) Introduction 1 1.1 ASYNCHRONOUSCIRCUITS 2 1.2 ASYNCHRONOUSON-CHIPNETWORKS 3 1.3 FAULT-TOLERANT ASYNCHRONOUS ON-CHIP NETWORKS 6 1.3.1 Protection for QDI Links 10 1.3.2 Deadlock Detection 10 1.3.3 Network Recovery 11 Chapter 2(cid:4) Asynchronous Circuits 13 2.1 CIRCUITCLASSIFICATION 13 2.1.1 Delay-Insensitive 14 2.1.2 Quasi-Delay-Insensitive 14 2.1.3 Speed-Independent 15 2.1.4 Relaxed QDI 16 2.1.5 Self-Timed 16 2.2 HANDSHAKEPROTOCOLS 17 2.2.1 Return-to-Zero 17 2.2.2 Non-Return-to-Zero 18 vii viii (cid:4) Contents 2.3 DATAENCODING 19 2.3.1 Non-Delay-Insensitive Codes 19 2.3.2 Delay-Insensitive Codes 20 2.3.2.1 1-of-n Encoding 20 2.3.2.2 m-of-n Encoding 21 2.3.2.3 Other DI Encoding 23 2.3.3 Code Evaluation 23 2.4 ASYNCHRONOUSPIPELINES 24 2.4.1 Bundled-Data Pipeline 25 2.4.2 Multi-Rail Pipeline 26 2.4.3 Performance Comparison 29 2.4.3.1 Pipeline Delay 29 2.4.3.2 Pipeline Throughput 29 2.4.3.3 Area and Power Consumption 30 2.5 IMPLEMENTATIONOFASYNCHRONOUS CIRCUITS 31 2.5.1 Functional Analysis 31 2.5.2 Common Circuit Components 34 2.5.2.1 Basic Components 34 2.5.2.2 Arbiters 39 2.5.2.3 Allocators 44 2.5.3 Metastability and Synchronization 47 2.5.4 Optimization with Traditional EDA Tools 49 2.5.4.1 Loop Elimination 50 2.5.4.2 Speed Optimization 53 Chapter 3(cid:4) Asynchronous Networks-on-Chip 57 3.1 CONCEPTSOFNETWORKS-ON-CHIP 58 3.1.1 Network Layer Model 59 3.1.2 Network Topology 60 Contents (cid:4) ix 3.1.3 Switching Techniques 63 3.1.3.1 Circuit Switching and Packet Switching 64 3.1.3.2 Virtual Channel 67 3.1.3.3 Other Flow Control Methods 70 3.1.3.4 Quality of Service 71 3.1.4 Routing Algorithms 72 3.1.4.1 Deterministic and Non-Deterministic 73 3.1.4.2 Deadlock and Livelock 75 3.2 ASYNCHRONOUSNETWORKS-ON-CHIP 78 3.2.1 Taxonomy of Asynchronous On-Chip Networks 78 3.2.2 Previous Asynchronous NoCs 82 3.2.2.1 SpiNNaker 82 3.2.2.2 ASPIN 83 3.2.2.3 QoS NoC 85 3.2.2.4 ANOC 85 3.2.2.5 MANGO 86 3.2.2.6 QNoC 87 Chapter 4(cid:4) OptimizingAsynchronousOn-ChipNetworks 89 4.1 CHANNELSLICING 89 4.1.1 Synchronization Overhead 90 4.1.2 Channel Slicing 92 4.1.3 Lookahead Pipeline 95 4.1.4 Channel Sliced Wormhole Router 97 4.1.4.1 Router Structure 98 4.1.4.2 Performance Evaluation 102