ASIC and FPGA Verification: A Guide to Component Modeling

337 Pages·2004·3.091 MB·English

by  Richard Munden

ASIC AND FPGA VERIFICATION:
A GUIDE TO COMPONENT MODELING
ABOUT THE AUTHOR
Richard Munden has been using and managing CAE systems since 1987. He has been
concerned with simulation and modeling issues for as long.
Richard co-founded the Free Model Foundry (http://eda.org/fmf/) in 1995 and is its
president and CEO. He has a day job as CAE/PCB manager at Siemens Ultrasound
(previously Acuson Corp) in Mountain View, California. Prior to joining Acuson, he
was a CAE manager at TRW in Redondo Beach, California. He is a well-known con-
tributor to several EDA users groups and industry conferences.
His primary focus over the years has been verification of board-level designs.
MAGPR 8/18/04 2:59 PM Page iii
ASIC AND FPGA
VERIFICATION:
A GUIDE TO
COMPONENT
MODELING
RICHARD MUNDEN
AMSTERDAM • BOSTON • HEIDELBERG • LONDON
NEW YORK • OXFORD • PARIS • SAN DIEGO
SAN FRANCISCO • SINGAPORE • SYDNEY • TOKYO
Morgan Kaufmann Publishers is an imprint of Elsevier
MAGPR 8/18/04 2:59 PM Page iv
The Morgan Kaufmann Series in Systems on Silicon
Series Editors: Peter Ashenden, Ashenden Designs Pty. Ltd. and Adelaide University, and
Wayne Wolf, Princeton University
The rapid growth of silicon technology and the demands of applications are
increasingly forcing electronics designers to take a systems-oriented approach to
design. This has led to new challenges in design methodology, design automation,
manufacture and test. The main challenges are to enhance designer productivity
and to achieve correctness on the first pass. The Morgan Kaufmann Series in
Systems on Silicon presents high quality, peer-reviewed books authored by leading
experts in the field who are uniquely qualified to address these issues.
The Designer’s Guide to VHDL, Second Edition
Peter J. Ashenden
The System Designer’s Guide to VHDL-AMS
Peter J. Ashenden, Gregory D. Peterson, and Darrell A. Teegarden
Readings in Hardware/Software Co-Design
Edited by Giovanni De Micheli, Rolf Ernst, and Wayne Wolf
Modeling Embedded Systems and SoCs
Axel Jantsch
Multiprocessor Systems-on-Chips
Edited by Wayne Wolf and Ahmed Jerraya
Forthcoming Titles
Rosetta User’s Guide: Model-Based Systems Design
Perry Alexander, Peter J. Ashenden, and David L. Barton
Rosetta Developer’s Guide: Semantics for Systems Design
Perry Alexander, Peter J. Ashenden, and David L. Barton
Functional Verification
Bruce Wile, John Goss, and Wolfgang Roesner
MAGPR 8/18/04 2:59 PM Page v
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Reprinted with permission from IEEE Std. 1076.4-2000, Copyright 2000 by IEEE, “IEEE
Standard VHDL Language Reference Manual”; IEEE Std. 1076.4-1995, Copyright 1995 by
IEEE, “Structure of a VITALModel”; and IEEEStd.1497-2001, Copyright 2001 by IEEE, “IEEE
Standard for Standard Delay Format (SDF) for the Electronic Design Process.” The IEEE dis-
claims any responsibility or liability resulting from the placement and use in the described
manner.
Library of Congress Cataloging-in-Publication Data:Application Submitted
ISBN: 0-12-510581-9
Printed in the United States of America
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CONTENTS
Preface xv
PART I INTRODUCTION 1
CHAPTER 1 INTRODUCTION TO BOARD-LEVEL VERIFICATION 3
1.1 Why Models are Needed 3
1.1.1 Prototyping 3
1.1.2 Simulation 4
1.2 Definition of a Model 5
1.2.1 Levels of Abstraction 6
1.2.2 Model Types 7
1.2.3 Technology-Independent Models 9
1.3 Design Methods and Models 10
1.4 How Models Fit in the FPGA/ASIC Design Flow 10
1.4.1 The Design/Verification Flow 11
1.5 Where to Get Models 13
1.6 Summary 14
CHAPTER 2 TOUR OF A SIMPLE MODEL 15
2.1 Formatting 15
2.2 Standard Interfaces 17
vii
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viii Contents
2.3 Model Delays 18
2.4 VITAL Additions 19
2.4.1 VITAL Delay Types 19
2.4.2 VITAL Attributes 20
2.4.3 VITAL Primitive Call 21
2.4.4 VITAL Processes 22
2.4.5 VitalPathDelays 24
2.5 Interconnect Delays 25
2.6 Finishing Touches 27
2.7 Summary 31
PART II RESOURCES AND STANDARDS 33
CHAPTER 3 VHDL PACKAGES FOR COMPONENT MODELS 35
3.1 STD_LOGIC_1164 35
3.1.1 Type Declarations 36
3.1.2 Functions 37
3.2 VITAL_Timing 37
3.2.1 Declarations 37
3.2.2 Procedures 38
3.3 VITAL_Primitives 39
3.3.1 Declarations 40
3.3.2 Functions and Procedures 40
3.4 VITAL_Memory 41
3.4.1 Memory Functionality 41
3.4.2 Memory Timing Specification 42
3.4.2 Memory_Timing Checks 42
3.5 FMF Packages 42
3.5.1 FMF gen_utils and ecl_utils 43
3.5.2 FMF ff_package 44
3.5.3 FMF Conversions 45
3.6 Summary 45
CHAPTER 4 AN INTRODUCTION TO SDF 47
4.1 Overview of an SDF File 47
4.1.1 Header 48
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Contents ix
4.1.2 Cell 50
4.1.3 Timing Specifications 50
4.2 SDF Capabilities 52
4.2.1 Circuit Delays 52
4.2.2 Timing Checks 55
4.3 Summary 58
CHAPTER 5 ANATOMY OF A VITAL MODEL 59
5.1 Level 0 Guidelines 59
5.1.1 Backannotation 60
5.1.2 Timing Generics 60
5.1.3 VitalDelayTypes 61
5.2 Level 1 Guidelines 63
5.2.1 Wire Delay Block 63
5.2.2 Negative Constraint Block 65
5.2.3 Processes 65
5.2.4 VITAL Primitives 70
5.2.5 Concurrent Procedure Section 70
5.3 Summary 70
CHAPTER 6 MODELING DELAYS 73
6.1 Delay Types and Glitches 73
6.1.1 Transport and Inertial Delays 73
6.1.2 Glitches 74
6.2 Distributed Delays 75
6.3 Pin-to-Pin Delays 75
6.4 Path Delay Procedures 76
6.5 Using VPDs 82
6.6 Generates and VPDs 83
6.7 Device Delays 83
6.8 Backannotating Path Delays 88
6.9 Interconnect Delays 89
6.10 Summary 90