ARM11 MPCore Processor - ARM - The Architecture For The Digital World

728 Pages·2008·4.32 MB·English

ARM11 MPCore™ Processor
Revision: r2p0
Technical Reference Manual
Copyright ©2005, 2006, 2008. All rights reserved.
ARM DDI 0360F
ARM11 MPCore Processor
Technical Reference Manual
Copyright ©2005, 2006, 2008. All rights reserved.
Release Information
The following changes have been made to this book.
Change history
Date Issue Confidentiality Change
02 February 2005 A Non-Confidential First release for r0p1
14 September 2005 B Non-Confidential First release for r0p2
16 December 2005 C Non-Confidential First release for r0p3
11 August 2006 D Non-Confidential First release for r1p0
14 February 2008 E Non-Confidential Second release for r1p0
15 October 2008 F Non-Confidential Unrestricted Access First release for r2p0
Proprietary Notice
Words and logos marked with ® or ™ are registered trademarks or trademarks of ARM Limited in the EU and
other countries, except as otherwise stated below in this proprietary notice. Other brands and names
mentioned herein may be the trademarks of their respective owners.
Neither the whole nor any part of the information contained in, or the product described in, this document
may be adapted or reproduced in any material form except with the prior written permission of the copyright
holder.
The product described in this document is subject to continuous developments and improvements. All
particulars of the product and its use contained in this document are given by ARM in good faith. However,
all warranties implied or expressed, including but not limited to implied warranties of merchantability, or
fitness for purpose, are excluded.
This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable
for any loss or damage arising from the use of any information in this document, or any error or omission in
such information, or any incorrect use of the product.
Figure13-1 on page13-2 reprinted with permission from IEEE Std. 1149.1-1990, IEEE Standard Test Access
Port and Boundary-Scan Architecture Copyright 2002, 2003, by IEEE. The IEEE disclaims any responsibility
or liability resulting from the placement and use in the described manner.
Some material in this document is based on IEEE Standard for Binary Floating-Point Arithmetic, ANSI/IEEE
Std 754-1985. The IEEE disclaims any responsibility or liability resulting from the placement and use in the
described manner.
Where the term ARM is used it means “ARM or any of its subsidiaries as appropriate”.
ii Copyright ©2005, 2006, 2008. All rights reserved. ARM DDI 0360F
Non-Confidential Unrestricted Access
Confidentiality Status
This document is Non-Confidential. The right to use, copy and disclose this document may be subject to
license restrictions in accordance with the terms of the agreement entered into by ARM and the party that
ARM delivered this document to.
Unrestricted Access is an ARM internal classification.
Product Status
The information in this document is final, that is for a developed product.
Web Address
http://www.arm.com
ARM DDI 0360F Copyright ©2005, 2006, 2008. All rights reserved. iii
Unrestricted Access Non-Confidential
iv Copyright ©2005, 2006, 2008. All rights reserved. ARM DDI 0360F
Non-Confidential Unrestricted Access
Contents
ARM11 MPCore Processor Technical Reference
Manual
Preface
About this book .......................................................................................... xxvi
Feedback .................................................................................................. xxxii
Chapter 1 Introduction
1.1 About the processor .................................................................................... 1-2
1.2 Extensions to ARMv6 .................................................................................. 1-4
1.3 MP11 CPU overview ................................................................................... 1-5
1.4 Debug and programming support ............................................................. 1-13
1.5 Power management .................................................................................. 1-18
1.6 Configurable options ................................................................................. 1-20
1.7 Pipeline stages .......................................................................................... 1-22
1.8 Typical pipeline operations ....................................................................... 1-24
1.9 MPCore architecture with Jazelle technology ........................................... 1-30
1.10 Parity checking support ............................................................................. 1-32
1.11 Product revisions ...................................................................................... 1-33
Chapter 2 Programmers Model
2.1 About the programmers model .................................................................... 2-2
2.2 Processor operating states ......................................................................... 2-3
ARM DDI 0360F Copyright ©2005, 2006, 2008. All rights reserved. v
Unrestricted Access Non-Confidential
Contents
2.3 Instruction length ........................................................................................ 2-4
2.4 Data types .................................................................................................. 2-5
2.5 Memory formats .......................................................................................... 2-6
2.6 Addresses in an MPCore system ............................................................... 2-8
2.7 Operating modes ...................................................................................... 2-10
2.8 Registers .................................................................................................. 2-11
2.9 The program status registers .................................................................... 2-17
2.10 Exceptions ................................................................................................ 2-24
Chapter 3 Control Coprocessor CP15
3.1 About control coprocessor CP15 ................................................................ 3-2
3.2 CP15 registers arranged by function .......................................................... 3-3
3.3 Summary of control coprocessor CP15 registers and operations .............. 3-6
3.4 Register descriptions ................................................................................ 3-11
3.5 Summary of CP15 instructions ................................................................. 3-77
Chapter 4 Unaligned and Mixed-Endian Data Access Support
4.1 About unaligned and mixed-endian support ............................................... 4-2
4.2 Unaligned access support .......................................................................... 4-3
4.3 Unaligned data access specification .......................................................... 4-7
4.4 Operation of unaligned accesses ............................................................. 4-18
4.5 Mixed-endian access support ................................................................... 4-22
4.6 Instructions to reverse bytes in a general-purpose register ...................... 4-25
4.7 Instructions to change the CPSR E bit ..................................................... 4-26
Chapter 5 Memory Management Unit
5.1 About the MMU ........................................................................................... 5-2
5.2 TLB organization ........................................................................................ 5-4
5.3 Memory access sequence .......................................................................... 5-7
5.4 Enabling and disabling the MMU ................................................................ 5-9
5.5 Memory access control ............................................................................. 5-11
5.6 Memory region attributes .......................................................................... 5-16
5.7 Memory attributes and types .................................................................... 5-21
5.8 MMU aborts .............................................................................................. 5-31
5.9 MMU fault checking .................................................................................. 5-33
5.10 Fault status and address .......................................................................... 5-38
5.11 Hardware page table translation ............................................................... 5-40
5.12 MMU descriptors ...................................................................................... 5-48
5.13 MMU software-accessible registers .......................................................... 5-59
5.14 MMU and Write Buffer .............................................................................. 5-64
Chapter 6 Program Flow Prediction
6.1 About program flow prediction .................................................................... 6-2
6.2 Branch prediction ........................................................................................ 6-4
6.3 Return stack ............................................................................................... 6-8
6.4 Memory Barriers ......................................................................................... 6-9
vi Copyright ©2005, 2006, 2008. All rights reserved. ARM DDI 0360F
Non-Confidential Unrestricted Access
Contents
Chapter 7 Level 1 Memory System
7.1 Coherency protocol ..................................................................................... 7-2
7.2 About the Level 1 data side memory system .............................................. 7-3
7.3 About the Level 1 instruction side memory system ................................... 7-10
7.4 TLB organization ....................................................................................... 7-11
Chapter 8 Level 2 Memory System
8.1 MPCore Level 2 interface ........................................................................... 8-2
8.2 L2 exclusive mode ...................................................................................... 8-6
8.3 Synchronization operations ......................................................................... 8-7
8.4 The ACLKEN signal .................................................................................... 8-9
Chapter 9 MPCore Private Memory Region
9.1 About the MPCore private memory region .................................................. 9-2
9.2 Timer and watchdog blocks ...................................................................... 9-15
Chapter 10 MPCore Distributed Interrupt Controller
10.1 About the Distributed Interrupt Controller .................................................. 10-2
10.2 Terminology .............................................................................................. 10-3
10.3 Interrupt Distributor ................................................................................... 10-4
10.4 CPU interrupt interfaces ............................................................................ 10-9
10.5 Interrupt Distributor Registers ................................................................. 10-10
10.6 CPU Interrupt Interface Registers ........................................................... 10-20
Chapter 11 Clocking, Resets, and Power Management
11.1 Clocking .................................................................................................... 11-2
11.2 Reset ......................................................................................................... 11-3
11.3 Reset modes ............................................................................................. 11-4
11.4 About power consumption control ............................................................. 11-6
11.5 Individual MP11 CPU power control ......................................................... 11-7
11.6 IEM support ............................................................................................. 11-11
11.7 Debug ..................................................................................................... 11-13
Chapter 12 Debug
12.1 Debug systems ......................................................................................... 12-2
12.2 About the debug unit ................................................................................. 12-4
12.3 Debug registers ......................................................................................... 12-6
12.4 CP14 registers reset ............................................................................... 12-25
12.5 CP14 debug instructions ......................................................................... 12-26
12.6 Debug events .......................................................................................... 12-29
12.7 Debug exception ..................................................................................... 12-33
12.8 Debug state ............................................................................................. 12-35
12.9 Debug communications channel ............................................................. 12-39
12.10 Debugging in a system with TLBs ........................................................... 12-40
12.11 Monitor debug-mode debugging ............................................................. 12-41
12.12 Halting debug-mode debugging .............................................................. 12-47
ARM DDI 0360F Copyright ©2005, 2006, 2008. All rights reserved. vii
Unrestricted Access Non-Confidential
Contents
12.13 External signals ...................................................................................... 12-49
Chapter 13 Debug Test Access Port
13.1 Debug Test Access Port and Halting debug-mode .................................. 13-2
13.2 Synchronizing RealView ICE .................................................................... 13-3
13.3 Entering debug state ................................................................................ 13-4
13.4 Exiting debug state ................................................................................... 13-5
13.5 DBGTAP controller overview .................................................................... 13-6
13.6 Debug registers ........................................................................................ 13-8
13.7 Using the Debug Test Access Port ......................................................... 13-23
13.8 Debug sequences ................................................................................... 13-33
13.9 Programming debug events ................................................................... 13-47
13.10 Monitor debug-mode debugging ............................................................. 13-49
Chapter 14 Trace Interface Port
14.1 About the ETM interface ........................................................................... 14-2
Chapter 15 Cycle Timings and Interlock Behavior
15.1 About cycle timings and interlock behavior .............................................. 15-3
15.2 Register interlock examples ..................................................................... 15-8
15.3 Data processing instructions .................................................................... 15-9
15.4 QADD, QDADD, QSUB, and QDSUB instructions ................................. 15-12
15.5 ARMv6 media data processing ............................................................... 15-13
15.6 ARMv6 Sum of Absolute Differences (SAD) .......................................... 15-15
15.7 Multiplies ................................................................................................. 15-16
15.8 Branches ................................................................................................ 15-18
15.9 Processor state updating instructions ..................................................... 15-19
15.10 Single load and store instructions ........................................................... 15-20
15.11 Load and store double instructions ......................................................... 15-23
15.12 Load and store multiple instructions ....................................................... 15-25
15.13 RFE and SRS instructions ...................................................................... 15-28
15.14 Synchronization instructions ................................................................... 15-29
15.15 Coprocessor instructions ........................................................................ 15-30
15.16 SWI, BKPT, Undefined, and Prefetch Aborted instructions .................... 15-31
15.17 Thumb instructions ................................................................................. 15-32
Chapter 16 Introduction to VFP
16.1 About the VFP11 coprocessor .................................................................. 16-2
16.2 Applications .............................................................................................. 16-3
16.3 Coprocessor interface .............................................................................. 16-4
16.4 VFP11 coprocessor pipelines ................................................................... 16-5
16.5 Modes of operation ................................................................................. 16-12
16.6 Short vector instructions ......................................................................... 16-15
16.7 Parallel execution of instructions ............................................................ 16-16
16.8 VFP11 treatment of branch instructions ................................................. 16-17
16.9 Writing optimal VFP11 code ................................................................... 16-18
viii Copyright ©2005, 2006, 2008. All rights reserved. ARM DDI 0360F
Non-Confidential Unrestricted Access
Contents
16.10 VFP11 revision information ..................................................................... 16-19
Chapter 17 VFP Register File
17.1 About the register file ................................................................................ 17-2
17.2 Register file internal formats ..................................................................... 17-3
17.3 Decoding the register file .......................................................................... 17-5
17.4 Loading operands from MPCore registers ................................................ 17-6
17.5 Maintaining consistency in register precision ............................................ 17-8
17.6 Data transfer between memory and VFP11 registers ............................... 17-9
17.7 Access to register banks in CDP operations ........................................... 17-11
Chapter 18 VFP Programmers Model
18.1 About the programmers model .................................................................. 18-2
18.2 Compliance with the IEEE 754 standard ................................................... 18-3
18.3 ARMv5TE coprocessor extensions ......................................................... 18-10
18.4 VFP11 system registers .......................................................................... 18-16
Chapter 19 VFP Instruction Execution
19.1 About instruction execution ....................................................................... 19-2
19.2 Serializing instructions .............................................................................. 19-3
19.3 Interrupting the VFP11 coprocessor ......................................................... 19-4
19.4 Forwarding ................................................................................................ 19-5
19.5 Hazards ..................................................................................................... 19-7
19.6 Operation of the scoreboards ................................................................... 19-8
19.7 Data hazards in full-compliance mode .................................................... 19-15
19.8 Data hazards in RunFast mode .............................................................. 19-19
19.9 Resource hazards ................................................................................... 19-20
19.10 Parallel execution .................................................................................... 19-23
19.11 Execution timing ...................................................................................... 19-25
Chapter 20 VFP Exception Handling
20.1 About exception processing ...................................................................... 20-2
20.2 Bounced instructions ................................................................................. 20-3
20.3 Support code ............................................................................................. 20-5
20.4 Exception processing ................................................................................ 20-8
20.5 Input Subnormal exception ..................................................................... 20-14
20.6 Invalid Operation exception .................................................................... 20-15
20.7 Division by Zero exception ...................................................................... 20-18
20.8 Overflow exception ................................................................................. 20-19
20.9 Underflow exception ............................................................................... 20-21
20.10 Inexact exception .................................................................................... 20-23
20.11 Input exceptions ...................................................................................... 20-24
20.12 Arithmetic exceptions .............................................................................. 20-25
Appendix A Signal Descriptions
A.1 AXI interface signals ................................................................................... A-2
ARM DDI 0360F Copyright ©2005, 2006, 2008. All rights reserved. ix
Unrestricted Access Non-Confidential
Contents
A.2 Interrupt lines .............................................................................................. A-8
A.3 Debug interface .......................................................................................... A-9
A.4 MBIST interface ........................................................................................ A-10
A.5 Power control interface ............................................................................. A-11
A.6 Miscellaneous signals ............................................................................... A-13
A.7 Scan test signals ...................................................................................... A-15
A.8 ETM interface signals ............................................................................... A-16
A.9 Parity signals ............................................................................................ A-18
Appendix B AC Characteristics
B.1 MPCore timing ............................................................................................ B-2
B.2 MPCore signal timing parameters .............................................................. B-3
Appendix C MBIST Controller and Dispatch Unit
C.1 About MBIST .............................................................................................. C-2
C.2 MBIST controller and MBIST dispatch unit ................................................. C-4
C.3 MBIST controller ......................................................................................... C-5
C.4 MBIST dispatch unit ................................................................................... C-6
C.5 MBIST signal descriptions .......................................................................... C-7
C.6 Shift register and fail datalog format ......................................................... C-12
C.7 Fail data log .............................................................................................. C-14
C.8 Testing RAM ............................................................................................. C-15
C.9 Testing MP11 CPU RAMs ........................................................................ C-17
C.10 Testing MP11 SCU RAM .......................................................................... C-24
C.11 Test patterns ............................................................................................. C-26
Appendix D Scan chain ordering with RVI
D.1 Scan chain ordering with RVI ..................................................................... D-2
Appendix E IEM
E.1 Purpose of IEM ........................................................................................... E-2
E.2 About AXI register slices ............................................................................ E-4
Appendix F Revisions
Glossary
x Copyright ©2005, 2006, 2008. All rights reserved. ARM DDI 0360F
Non-Confidential Unrestricted Access