ARM System Memory Management Unit Architecture Specification SMMU architecture version 2.0

372 Pages·2016·2.24 MB·English

ARM System Memory Management
®
Unit Architecture Specification
SMMU architecture version 2.0
Copyright ©2012, 2013, 2015, 2016 ARM Limited. All rights reserved.
ARM IHI 0062D.c (ID070116)
ARM System Memory Management Unit Architecture Specification
SMMU architecture version 2.0
Copyright ©2012, 2013, 2015, 2016 ARM Limited. All rights reserved.
Release Information
The following changes have been made to this document.
Change History
Date Issue Confidentiality Change
23 March 2012 A Confidential Beta Issue A. Beta release for architecture version 1.0.
18 December 2012 B Non-Confidential Issue B. Final release for architecture version 1.0.
16 September 2013 C.a Non-Confidential Beta Issue C. Beta release for architecture version 2.0.
13 January 2015 D Non-Confidential Issue D full release for architecture version 2.0 with architecture extensions.
28 January 2015 D.a Non-Confidential Non-Confidential Issue D full release. Architecture version 2.0 with
architecture extensions.
15 July 2015 D.b Non-Confidential Issue D.b update with corrections and clarifications.
30 June 2016 D.c Non-Confidential Issue D.c update with corrections and clarifications.
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Contents
ARM System Memory Management Unit
Architecture Specification SMMU architecture
version 2.0
Preface
About this specification ............................................................................................... x
Using this specification ............................................................................................... xi
Conventions .............................................................................................................. xiii
Additional reading ..................................................................................................... xiv
Feedback .................................................................................................................. xv
Chapter 1 Introduction
1.1 About the ARM System MMU architecture ............................................................. 1-18
1.2 About the SMMU .................................................................................................... 1-21
1.3 ARM PE Exception levels and Execution states .................................................... 1-23
1.4 ARM translation regimes ........................................................................................ 1-24
1.5 SMMU translation schemes ................................................................................... 1-28
1.6 SMMU address support ......................................................................................... 1-36
Chapter 2 SMMU Operation
2.1 Overview of SMMU operation ................................................................................ 2-42
2.2 Security State Determination (SSD) ....................................................................... 2-50
2.3 Context determination ............................................................................................ 2-52
2.4 Memory type and shareability attribute determination ............................................ 2-59
2.5 TLB operation ......................................................................................................... 2-72
2.6 Translation context ................................................................................................. 2-75
2.7 Translation and protection checks ......................................................................... 2-84
2.8 Hypervisor contexts (HYPC) .................................................................................. 2-86
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2.9 Monitor contexts (MONC) ....................................................................................... 2-89
2.10 E2H contexts (E2HC) ............................................................................................. 2-90
Chapter 3 The Fault Model
3.1 Overview of fault types ........................................................................................... 3-94
3.2 Fault-handling terminology ..................................................................................... 3-95
3.3 Handling multiple memory faults ............................................................................ 3-96
3.4 Recording memory attributes ................................................................................. 3-97
3.5 Recording stage 1 followed by stage 2 translation faults ....................................... 3-98
3.6 Fault interrupts ..................................................................................................... 3-100
3.7 Context faults ....................................................................................................... 3-102
3.8 Global faults ......................................................................................................... 3-114
3.9 Configuration access ............................................................................................ 3-119
3.10 External faults ...................................................................................................... 3-120
3.11 Reporting exclusive access transactions ............................................................. 3-122
3.12 Fault behavior in virtualized context banks .......................................................... 3-123
Chapter 4 Address Translation Operations
4.1 About address translation operations ................................................................... 4-126
4.2 Address translation registers in a stage 1 translation context .............................. 4-127
4.3 Address translation registers in the global address space ................................... 4-130
Chapter 5 Coherency Issues and Cache Maintenance Operations
5.1 Updating the state of a context bank .................................................................... 5-134
5.2 Translation table walk coherency ......................................................................... 5-135
5.3 Broadcast TLB maintenance operations .............................................................. 5-136
5.4 TLB maintenance operations ............................................................................... 5-137
5.5 Cache maintenance operations ........................................................................... 5-141
Chapter 6 SMMU Performance Monitors Extension
6.1 About the SMMU Performance Monitors Extension ............................................. 6-146
6.2 The register map .................................................................................................. 6-147
6.3 Event classes ....................................................................................................... 6-148
6.4 StreamID groups .................................................................................................. 6-149
6.5 Counter groups .................................................................................................... 6-150
6.6 Event filtering ....................................................................................................... 6-151
6.7 Translation context bank assignment ................................................................... 6-152
6.8 Event counter overflow interrupt .......................................................................... 6-153
Chapter 7 SMMU Support for Two Security States
7.1 Sharing resources between Secure and Non-secure domains ............................ 7-156
7.2 Providing SMMU support for only a single Security state .................................... 7-157
7.3 Providing SMMU support for two Security states ................................................. 7-158
Chapter 8 SMMU Address Space
8.1 About the SMMU address space ......................................................................... 8-164
8.2 The global address space .................................................................................... 8-165
8.3 The translation context bank address space ........................................................ 8-167
Chapter 9 SMMU Global Register Space 0
9.1 SMMU Global Register Space 0 register summary .............................................. 9-170
9.2 Reset values ........................................................................................................ 9-175
9.3 Secure alias for Non-secure registers .................................................................. 9-177
9.4 Memory attribute, MemAttr ................................................................................... 9-179
9.5 Multi-format registers and reserved fields ............................................................ 9-180
9.6 SMMU Global Register Space 0 register descriptions ......................................... 9-181
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Chapter 10 SMMU Global Register Space 1
10.1 SMMU Global Register Space 1 register summary ............................................ 10-240
10.2 SMMU Global Register Space 1 register descriptions ....................................... 10-241
Chapter 11 SMMU IMPLEMENTATION DEFINED Address Space
11.1 About the SMMU IMPLEMENTATION DEFINED address space ...................... 11-252
Chapter 12 SMMU Performance Monitors Extension Register Map
12.1 SMMU Performance Monitors Extension register summary .............................. 12-254
12.2 SMMU Performance Monitors Extension register descriptions .......................... 12-256
Chapter 13 The Security State Determination Address Space
13.1 SMMU SSD address space ................................................................................ 13-272
Chapter 14 Extended Stream Matching Extension
14.1 About the Extended Stream Match extension .................................................... 14-276
14.2 Extended Stream Match Extension registers ..................................................... 14-279
Chapter 15 StreamID Compressed Indexing Extension
15.1 About the StreamID Compressed Indexing Extension ....................................... 15-282
15.2 StreamID Compressed Indexing Extension registers ......................................... 15-284
Chapter 16 Stage 1 Translation Context Bank Format
16.1 Stage 1 translation context bank address space ............................................... 16-286
16.2 Reset values ...................................................................................................... 16-290
16.3 Memory attribute indirection ............................................................................... 16-291
16.4 Multi-format registers and reserved fields .......................................................... 16-293
16.5 Stage 1 translation context bank register descriptions ....................................... 16-294
Chapter 17 Stage 2 Translation Context Bank Format
17.1 Stage 1 and stage 2 context bank format differences ........................................ 17-344
17.2 Stage 2 translation context bank address space ............................................... 17-345
17.3 Stage 2 translation context bank register descriptions ....................................... 17-348
Appendix A Register Names
A.1 Summary of corresponding SMMU and ARM registers ...................................... A-364
Glossary
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Preface
This preface introduces the ARM® System Memory Management Unit Architecture Specification. It contains the
following sections:
• About this specification on pagex.
• Using this specification on pagexi.
• Conventions on pagexiii.
• Additional reading on pagexiv.
• Feedback on pagexv.
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Preface
About this specification
About this specification
This specification introduces the ARM System MMU (SMMU) architecture.
Intended audience
This specification is written for readers who are familiar with system memory management concepts, but who do
not necessarily have any experience of the ARM architecture.
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