ARM microprocessor systems: Cortex-M architecture, programming, and interfacing

515 Pages·2017·22.15 MB·English

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ARM®
Microprocessor Systems
Cortex®-M Architecture, Programming, and Interfacing
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ARM®
Microprocessor Systems
Cortex®-M Architecture, Programming, and Interfacing
Muhammad Tahir and Kashif Javed
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CRC Press
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Library of Congress Cataloging‑in‑Publication Data
Library of Congress Cataloging-in-Publication Data
Names: Tahir, Muhammad (Electrical engineer), author. | Javed, Kashif, author.
Title: ARM microprocessor systems : cortex-M architecture, programming, and
interfacing / Muhammad Tahir and Kashif Javed.
Description: Boca Raton : Taylor & Francis, CRC Press, 2017.
Identifiers: LCCN 2016038555| ISBN 9781482259384 (hb : alk. paper) | ISBN
9781482259391 (electronic)
Subjects: LCSH: ARM microprocessors--Programming.
Classification: LCC QA76.6 .T337 2017 | DDC 005.1/8--dc23
LC record available at https://lccn.loc.gov/2016038555
Visit the Taylor & Francis Web site at
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and the CRC Press Web site at
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Contents
Preface xiii
1 Introduction 1
1.1 What’s the Book About . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Embedded Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2.1 Examples of Embedded Systems . . . . . . . . . . . . . . . . 4
1.2.2 Design Parameters of Embedded Systems . . . . . . . . . . . 5
1.3 Microcontrollers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.4 Memory: Information Storage Device . . . . . . . . . . . . . . . . . . 7
1.4.1 Read Only Memory . . . . . . . . . . . . . . . . . . . . . . . 8
1.4.2 Random Access Memory . . . . . . . . . . . . . . . . . . . . 9
1.4.3 Aligned and Unaligned Memory Accesses . . . . . . . . . . . 10
1.5 The Microprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.6 Microprocessor Architecture Classification . . . . . . . . . . . . . . . 12
1.6.1 Instruction Set Architecture . . . . . . . . . . . . . . . . . . 13
1.6.2 Memory Interface-Based Architecture Classification . . . . . 16
1.6.3 Performance Comparison of Different Architectures . . . . . 16
1.7 Software System and Development Tools . . . . . . . . . . . . . . . . 18
1.7.1 Software Sub-Systems . . . . . . . . . . . . . . . . . . . . . . 18
1.7.2 Software Development Tools . . . . . . . . . . . . . . . . . . 20
1.8 Debugging Tools and Techniques . . . . . . . . . . . . . . . . . . . . 21
1.8.1 Manual Methods . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.8.2 Software-Only Methods . . . . . . . . . . . . . . . . . . . . . 24
1.8.3 Software-Hardware Debugging Tools . . . . . . . . . . . . . . 25
1.9 Summary of Key Concepts . . . . . . . . . . . . . . . . . . . . . . . . 29
I Architecture 33
2 Cortex-M Architecture 35
2.1 Introduction to Cortex-M Microcontroller . . . . . . . . . . . . . . . 36
2.2 Microprocessor Architecture . . . . . . . . . . . . . . . . . . . . . . . 37
2.2.1 ARM Instruction Set Architecture . . . . . . . . . . . . . . . 39
2.2.2 Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2.2.3 Processor Operating Modes . . . . . . . . . . . . . . . . . . . 45
2.2.4 Interrupts and Processor Reset Sequence . . . . . . . . . . . 47
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vi CONTENTS
2.2.5 Pipelined Architecture and Data Path . . . . . . . . . . . . . 48
2.2.6 Memory Address Map . . . . . . . . . . . . . . . . . . . . . . 51
2.3 Nested Interrupt Vector Controller . . . . . . . . . . . . . . . . . . . 52
2.4 Bus System and Bus Matrix . . . . . . . . . . . . . . . . . . . . . . . 53
2.5 Memory and Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . 55
2.5.1 Memory Endianness . . . . . . . . . . . . . . . . . . . . . . . 56
2.5.2 Bit Banding . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
2.5.3 System Stack Architecture . . . . . . . . . . . . . . . . . . . 61
2.6 Debug System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
2.6.1 AHB Access Port . . . . . . . . . . . . . . . . . . . . . . . . 64
2.6.2 Flash Patch and Breakpoint Unit (FPB) . . . . . . . . . . . 64
2.6.3 Data Watchpoint and Trace (DWT) . . . . . . . . . . . . . . 65
2.6.4 Instrumentation Trace Macrocell (ITM) . . . . . . . . . . . . 66
2.6.5 Embedded Trace Macrocell (ETM) . . . . . . . . . . . . . . 66
2.6.6 Trace Port Interface Unit (TPIU) . . . . . . . . . . . . . . . 66
2.6.7 Memory Protection Unit . . . . . . . . . . . . . . . . . . . . 66
2.7 Summary of Key Concepts . . . . . . . . . . . . . . . . . . . . . . . . 67
3 Exceptions and Interrupts Architecture 71
3.1 The Cortex-M Exceptions and Interrupts . . . . . . . . . . . . . . . 72
3.1.1 Nested Vectored Interrupt Controller . . . . . . . . . . . . . 72
3.1.2 Exception Types . . . . . . . . . . . . . . . . . . . . . . . . . 72
3.2 Exception and Interrupt Priority . . . . . . . . . . . . . . . . . . . . 73
3.2.1 Interrupt States . . . . . . . . . . . . . . . . . . . . . . . . . 76
3.3 Interrupt Configuration . . . . . . . . . . . . . . . . . . . . . . . . . 77
3.3.1 Basic Interrupt Configuration . . . . . . . . . . . . . . . . . 77
3.3.2 Interrupt Masking . . . . . . . . . . . . . . . . . . . . . . . . 78
3.3.3 Setting Up Interrupt Vector Table . . . . . . . . . . . . . . . 79
3.3.4 Configuring an Interrupt . . . . . . . . . . . . . . . . . . . . 81
3.4 Handling of Exceptions or Interrupts . . . . . . . . . . . . . . . . . . 81
3.4.1 Register Stacking in Response to Interrupt Occurrence . . . 82
3.4.2 Updating Registers . . . . . . . . . . . . . . . . . . . . . . . 84
3.4.3 Exception Exit or Return . . . . . . . . . . . . . . . . . . . . 86
3.4.4 Interrupt Latency . . . . . . . . . . . . . . . . . . . . . . . . 87
3.5 Interrupts Tail Chaining . . . . . . . . . . . . . . . . . . . . . . . . . 88
3.6 Interrupt Nesting with Multi-Level Priority . . . . . . . . . . . . . . 89
3.6.1 Multi-Level Interrupt Priority . . . . . . . . . . . . . . . . . 89
3.6.2 Interrupt Pending Behavior . . . . . . . . . . . . . . . . . . . 90
3.7 Summary of Key Concepts . . . . . . . . . . . . . . . . . . . . . . . . 91
II Programming 95
4 Basics of Assembly Programming 97
4.1 Introduction to ARM Instruction Sets . . . . . . . . . . . . . . . . . 97
4.2 Cortex-M Assembly Programming Basics . . . . . . . . . . . . . . . 98
4.2.1 ADD and MOV Data Processing Instructions . . . . . . . . . 100
4.2.2 LDR and STR Memory Access Instructions . . . . . . . . . . 101
4.2.3 Unconditional- and Combined Compare-Branch Instructions 102
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4.3 Our First Assembly Program . . . . . . . . . . . . . . . . . . . . . . 102
4.3.1 Assembler Directives . . . . . . . . . . . . . . . . . . . . . . 104
4.3.2 Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . 106
4.3.3 Complete First Assembly Program . . . . . . . . . . . . . . . 109
4.3.4 Assembly Program for Multiplication . . . . . . . . . . . . . 110
4.4 Instruction Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
4.4.1 16-bit Instruction Encoding . . . . . . . . . . . . . . . . . . . 112
4.4.2 32-bit Instruction Encoding . . . . . . . . . . . . . . . . . . . 112
4.4.3 Visualizing Instruction Encoding . . . . . . . . . . . . . . . . 113
4.5 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
4.6 Summary of Key Concepts . . . . . . . . . . . . . . . . . . . . . . . . 115
5 Data Processing Instructions 121
5.1 Shift, Rotate, and Logical Instructions . . . . . . . . . . . . . . . . . 122
5.1.1 Shift and Rotate Instructions . . . . . . . . . . . . . . . . . . 122
5.1.2 Logical Instructions . . . . . . . . . . . . . . . . . . . . . . . 128
5.1.3 Applications of Bit Operations . . . . . . . . . . . . . . . . . 130
5.2 Basic Arithmetic Instructions . . . . . . . . . . . . . . . . . . . . . . 131
5.2.1 Addition and Subtraction Instructions . . . . . . . . . . . . . 132
5.2.2 Multiply and Divide Instructions . . . . . . . . . . . . . . . . 134
5.3 Data Movement Instructions . . . . . . . . . . . . . . . . . . . . . . . 138
5.4 Bitfield Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
5.4.1 Bit and Byte Reversal Instructions. . . . . . . . . . . . . . . 141
5.4.2 Bitfield Clear and Insert Instructions . . . . . . . . . . . . . 141
5.4.3 Bitfield Extract Instructions . . . . . . . . . . . . . . . . . . 144
5.4.4 Miscellaneous Bitfield Instructions . . . . . . . . . . . . . . . 144
5.5 Test and Compare Instructions . . . . . . . . . . . . . . . . . . . . . 147
5.6 Saturating Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . 148
5.7 Summary of Key Concepts . . . . . . . . . . . . . . . . . . . . . . . . 152
6 Memory Access Instructions 157
6.1 When to Interact with Memory . . . . . . . . . . . . . . . . . . . . . 157
6.2 Load and Store Instructions . . . . . . . . . . . . . . . . . . . . . . . 158
6.2.1 Immediate Offset Addressing . . . . . . . . . . . . . . . . . . 159
6.2.2 Register Offset Addressing . . . . . . . . . . . . . . . . . . . 164
6.2.3 Aligned and Unaligned Memory Accesses . . . . . . . . . . . 165
6.2.4 Unprivileged Load and Store Instructions . . . . . . . . . . . 166
6.3 LDR with PC-Relative Addressing Mode . . . . . . . . . . . . . . . . 167
6.3.1 How Does LDR with PC-Relative Addressing Work?. . . . . 167
6.3.2 Generating 32-Bit Constants with LDR Instruction . . . . . 168
6.3.3 Literal Pools . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
6.4 The ADR Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . 172
6.4.1 Comparison of LDR and ADR Pseudo-Instructions . . . . . 172
6.5 Double and Multiple Word Memory Accesses . . . . . . . . . . . . . 174
6.5.1 Double Word Load and Store Instructions. . . . . . . . . . . 174
6.5.2 Multiple Word Load and Store Instructions . . . . . . . . . . 175
6.6 Stack Memory Access with PUSH and POP . . . . . . . . . . . . . . 177
6.6.1 Why Do We Need a Stack? . . . . . . . . . . . . . . . . . . . 180
6.6.2 Rules for Stack Usage . . . . . . . . . . . . . . . . . . . . . . 181
6.7 Summary of Key Concepts . . . . . . . . . . . . . . . . . . . . . . . . 182
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7 Branch and Control Instructions 187
7.1 Introduction to Conditional Execution . . . . . . . . . . . . . . . . . 188
7.2 Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
7.2.1 Implementing Function Calls . . . . . . . . . . . . . . . . . . 191
7.2.2 Implementing Branch Operations Indirectly . . . . . . . . . . 193
7.3 Conditional Branch Execution . . . . . . . . . . . . . . . . . . . . . . 193
7.3.1 Single-Flag Branch Instructions . . . . . . . . . . . . . . . . 194
7.3.2 Unsigned Conditional Branch Instructions . . . . . . . . . . 196
7.3.3 Signed Conditional Branch . . . . . . . . . . . . . . . . . . . 197
7.4 Implementing Branching Structures . . . . . . . . . . . . . . . . . . . 199
7.4.1 Implementing if . . . . . . . . . . . . . . . . . . . . . . . . . 199
7.4.2 Implementing if-else . . . . . . . . . . . . . . . . . . . . . . . 199
7.5 Implementing Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
7.5.1 The for Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
7.5.2 The while loop . . . . . . . . . . . . . . . . . . . . . . . . . . 201
7.6 Implementing Switch-Case . . . . . . . . . . . . . . . . . . . . . . . . 202
7.7 Combined Compare and Conditional Branch . . . . . . . . . . . . . . 203
7.8 Recursive Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
7.9 Passing Parameters to Functions . . . . . . . . . . . . . . . . . . . . 206
7.10 If-Then Conditional Instruction Block . . . . . . . . . . . . . . . . . 208
7.10.1 Illustrating the Advantages of IT Instruction . . . . . . . . . 211
7.11 Table Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . . 213
7.12 Special Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
7.12.1 MSR and MRS Instructions . . . . . . . . . . . . . . . . . . 215
7.12.2 CPS Instruction . . . . . . . . . . . . . . . . . . . . . . . . . 215
7.13 Summary of Key Concepts . . . . . . . . . . . . . . . . . . . . . . . . 216
III Interfacing 221
8 Fundamentals of Input-Output Interfacing 223
8.1 Basic Microcontroller GPIO Interfacing . . . . . . . . . . . . . . . . 224
8.1.1 GPIO Features . . . . . . . . . . . . . . . . . . . . . . . . . . 225
8.1.2 Multiplexing Functionalities on GPIO Pin . . . . . . . . . . 226
8.2 Cortex-M-Based TM4C123 Microcontroller . . . . . . . . . . . . . . 226
8.2.1 TM4C123 Microcontroller Block Diagram . . . . . . . . . . . 228
8.2.2 TM4C123 Microcontroller GPIOs . . . . . . . . . . . . . . . 228
8.2.3 Minimum Connectivity for TM4C123 . . . . . . . . . . . . . 228
8.2.4 The Hardware Development Board. . . . . . . . . . . . . . . 230
8.3 TM4C123 Microcontroller Peripherals . . . . . . . . . . . . . . . . . 232
8.3.1 Peripherals on the Memory Map . . . . . . . . . . . . . . . . 233
8.4 Configuring Microcontroller Pins as GPIOs . . . . . . . . . . . . . . 234
8.4.1 Clock and Bus Configuration . . . . . . . . . . . . . . . . . . 235
8.4.2 Mode Control Configuration . . . . . . . . . . . . . . . . . . 236
8.4.3 Pad Control Configuration . . . . . . . . . . . . . . . . . . . 237
8.4.4 Data Control Configuration . . . . . . . . . . . . . . . . . . . 238
8.4.5 GPIO Configuration for Alternate Functionality . . . . . . . 241
8.4.6 Configuring KEIL Tools for Hardware Debugging . . . . . . 242
8.5 Input-Output Interfacing for LED and Switch . . . . . . . . . . . . . 242
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8.5.1 Output Interfacing for LED. . . . . . . . . . . . . . . . . . . 243
8.5.2 Input Interfacing for Switch . . . . . . . . . . . . . . . . . . 246
8.6 Seven-Segment LED Interfacing . . . . . . . . . . . . . . . . . . . . . 250
8.6.1 Time Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . 251
8.7 Keypad Interfacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
8.8 Interfacing an LCD Module . . . . . . . . . . . . . . . . . . . . . . . 261
8.8.1 LCD Module Pin Functions . . . . . . . . . . . . . . . . . . . 261
8.8.2 Interfacing LCD Module with TM4C123 . . . . . . . . . . . 262
8.9 Summary of Key Concepts . . . . . . . . . . . . . . . . . . . . . . . . 268
9 I/O Synchronization and Interrupt Programming 273
9.1 Why Synchronization is Needed . . . . . . . . . . . . . . . . . . . . . 273
9.2 Introduction to Input-Output Synchronization. . . . . . . . . . . . . 274
9.2.1 Input Device Synchronization. . . . . . . . . . . . . . . . . . 275
9.2.2 Output Device Synchronization . . . . . . . . . . . . . . . . 276
9.3 Methods for Input-Output Synchronization . . . . . . . . . . . . . . 276
9.3.1 Blind Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
9.3.2 Polling Based Methods . . . . . . . . . . . . . . . . . . . . . 279
9.3.3 Interrupt-Driven Methods . . . . . . . . . . . . . . . . . . . . 281
9.4 Types of Exceptions or Interrupts . . . . . . . . . . . . . . . . . . . . 283
9.4.1 Synchronous Exceptions . . . . . . . . . . . . . . . . . . . . . 283
9.4.2 Asynchronous Exceptions . . . . . . . . . . . . . . . . . . . . 283
9.5 Configuring Interrupts for Cortex-M Devices. . . . . . . . . . . . . . 285
9.5.1 Processor Interrupt Configuration on TM4C123 . . . . . . . 286
9.5.2 NVIC Configuration on TM4C123 . . . . . . . . . . . . . . . 287
9.5.3 Device Interrupt Configuration on TM4C123 . . . . . . . . . 290
9.6 Interrupt-Based Switch/Keypad Interfacing . . . . . . . . . . . . . . 294
9.6.1 Switch Interfacing Using Interrupts . . . . . . . . . . . . . . 294
9.6.2 Interrupt-Driven Keypad Interfacing . . . . . . . . . . . . . . 296
9.7 Summary of Key Concepts . . . . . . . . . . . . . . . . . . . . . . . . 301
10 Timing Interfaces 305
10.1 Basics of Timing Interfaces . . . . . . . . . . . . . . . . . . . . . . . 305
10.2 Clocking a Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . 306
10.2.1 Phase Lock Loop. . . . . . . . . . . . . . . . . . . . . . . . . 307
10.2.2 PLL as Frequency Multiplier . . . . . . . . . . . . . . . . . . 308
10.3 TM4C123 Clock and Frequency Configuration . . . . . . . . . . . . . 309
10.3.1 Default Clock Source and Frequency Configuration . . . . . 309
10.3.2 Configuring Clock Frequency . . . . . . . . . . . . . . . . . . 311
10.4 Timer Basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
10.4.1 Timer Resolution and Range . . . . . . . . . . . . . . . . . . 315
10.5 TM4C123 Timing Interfaces and Systick Timer . . . . . . . . . . . . 316
10.5.1 Systick Timer . . . . . . . . . . . . . . . . . . . . . . . . . . 316
10.6 Timer as Input Device . . . . . . . . . . . . . . . . . . . . . . . . . . 319
10.6.1 Timer as External Event Counter . . . . . . . . . . . . . . . 320
10.6.2 Timer as Input Capture Device. . . . . . . . . . . . . . . . . 320
10.7 Frequency Measurement Using Timers . . . . . . . . . . . . . . . . . 322
10.7.1 Period Measurement . . . . . . . . . . . . . . . . . . . . . . . 322
10.7.2 Cycle Counting . . . . . . . . . . . . . . . . . . . . . . . . . 324
10.8 Timer as Output Device . . . . . . . . . . . . . . . . . . . . . . . . . 325
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