ARM Cortex-M7 Processor Technical Reference Manual

145 Pages·2014·0.99 MB·English

ARM® Cortex®-M7 Processor
Revision r0p2
Technical Reference Manual
Copyright ©2014 ARM. All rights reserved.
ARM DDI 0489B (ID120914)
ARM Cortex-M7 Processor
Technical Reference Manual
Copyright ©2014 ARM. All rights reserved.
Release Information
The following changes have been made to this book.
Change history
Date Issue Confidentiality Change
25 April 2014 A Confidential First release for r0p0
05 December 2014 B Non-Confidential First release for r0p2
Proprietary Notice
Words and logos marked with ® or ™ are registered trademarks or trademarks of ARM® in the EU and other countries,
except as otherwise stated below in this proprietary notice. Other brands and names mentioned herein may be the
trademarks of their respective owners.
Neither the whole nor any part of the information contained in, or the product described in, this document may be
adapted or reproduced in any material form except with the prior written permission of the copyright holder.
The product described in this document is subject to continuous developments and improvements. All particulars of the
product and its use contained in this document are given by ARM in good faith. However, all warranties implied or
expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded.
This document is intended only to assist the reader in the use of the product. ARM shall not be liable for any loss or
damage arising from the use of any information in this document, or any error or omission in such information, or any
incorrect use of the product.
Where the term ARM is used it means “ARM or any of its subsidiaries as appropriate”.
Confidentiality Status
This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license
restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this
document to.
Product Status
The information in this document is final, that is for a developed product.
Web Address
http://www.arm.com
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Contents
ARM Cortex-M7 Processor Technical Reference
Manual
Preface
About this book ........................................................................................................... vi
Feedback ..................................................................................................................... x
Chapter 1 Introduction
1.1 About the Cortex-M7 processor ............................................................................... 1-2
1.2 Component blocks ................................................................................................... 1-6
1.3 Interfaces ............................................................................................................... 1-10
1.4 Supported standards ............................................................................................. 1-12
1.5 Design process ...................................................................................................... 1-13
1.6 Documentation ....................................................................................................... 1-14
1.7 Product revisions ................................................................................................... 1-15
Chapter 2 Programmers Model
2.1 About the programmers model ................................................................................ 2-2
2.2 Modes of operation and execution ........................................................................... 2-3
2.3 Instruction set summary ........................................................................................... 2-4
2.4 System address map ............................................................................................... 2-5
2.5 Exclusive monitor ..................................................................................................... 2-7
2.6 Processor core registers .......................................................................................... 2-8
2.7 Exceptions ............................................................................................................... 2-9
Chapter 3 System Control
3.1 About system control ............................................................................................... 3-2
3.2 Register summary .................................................................................................... 3-3
3.3 Register descriptions ............................................................................................... 3-6
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Contents
Chapter 4 Initialization
4.1 About Initialization .................................................................................................... 4-2
Chapter 5 Memory System
5.1 About the memory system ....................................................................................... 5-2
5.2 Fault handling .......................................................................................................... 5-3
5.3 Memory types and memory system behavior .......................................................... 5-5
5.4 AXIM interface ......................................................................................................... 5-6
5.5 AHB peripheral interface ........................................................................................ 5-22
5.6 AHB slave interface ............................................................................................... 5-30
5.7 TCM interfaces ...................................................................................................... 5-33
5.8 L1 caches .............................................................................................................. 5-35
Chapter 6 Memory Protection Unit
6.1 About the MPU ........................................................................................................ 6-2
6.2 MPU functional description ...................................................................................... 6-3
6.3 MPU programmers model ........................................................................................ 6-4
Chapter 7 Nested Vectored Interrupt Controller
7.1 About the NVIC ........................................................................................................ 7-2
7.2 NVIC functional description ..................................................................................... 7-3
7.3 NVIC programmers model ....................................................................................... 7-4
Chapter 8 Floating Point Unit
8.1 About the FPU ......................................................................................................... 8-2
8.2 FPU functional description ....................................................................................... 8-3
8.3 FPU programmers model ........................................................................................ 8-5
Chapter 9 Debug
9.1 About debug ............................................................................................................ 9-2
9.2 About the AHBD interface ........................................................................................ 9-7
9.3 About the FPB ......................................................................................................... 9-8
Chapter 10 Cross Trigger Interface
10.1 About the CTI ......................................................................................................... 10-2
10.2 Cortex-M7 CTI functional description .................................................................... 10-3
10.3 CTI programmers model ........................................................................................ 10-5
Chapter 11 Data Watchpoint and Trace Unit
11.1 About the DWT ...................................................................................................... 11-2
11.2 DWT functional description .................................................................................... 11-3
11.3 DWT programmers model ..................................................................................... 11-4
Chapter 12 Instrumentation Trace Macrocell Unit
12.1 About the ITM ........................................................................................................ 12-2
12.2 ITM functional description ...................................................................................... 12-3
12.3 ITM programmers model ....................................................................................... 12-4
Chapter 13 Fault detection and handling
13.1 About fault detection and handling ........................................................................ 13-2
13.2 Cache RAM protection ........................................................................................... 13-3
13.3 Logic protection ..................................................................................................... 13-6
Appendix A Revisions
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Preface
This preface introduces the Cortex-M7 Processor Technical Reference Manual (TRM). It
contains the following sections:
• About this book on pagevi.
• Feedback on pagex.
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Preface
About this book
This book is for the Cortex-M7 processor.
Product revision status
The rnpn identifier indicates the revision status of the product described in this manual, where:
rn Identifies the major revision of the product.
pn Identifies the minor revision or modification status of the product.
Intended audience
This manual is written to help system designers, system integrators, verification engineers, and
software programmers who are implementing a System-on-Chip (SoC) device based on the
Cortex-M7 processor.
Using this book
This book is organized into the following chapters:
Chapter1 Introduction
Read this for a description of the components of the processor, and of the product
documentation.
Chapter2 Programmers Model
Read this for a description of the processor register set, modes of operation, and
other information for programming the processor.
Chapter3 System Control
Read this for a description of the registers and programmers model for system
control.
Chapter4 Initialization
Read this for a description of how to initialize the processor.
Chapter5 Memory System
Read this for a description of the processor memory system.
Chapter6 Memory Protection Unit
Read this for a description of the Memory Protection Unit (MPU).
Chapter7 Nested Vectored Interrupt Controller
Read this for a description of the interrupt processing and control.
Chapter8 Floating Point Unit
Read this for a description of the Floating Point Unit (FPU).
Chapter9 Debug
Read this for information about debugging and testing the processor.
Chapter10 Cross Trigger Interface
Read this for information about how the Cross Trigger Interface (CTI) can be
configured.
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Preface
Chapter11 Data Watchpoint and Trace Unit
Read this for a description of the Data Watchpoint and Trace (DWT) unit.
Chapter12 Instrumentation Trace Macrocell Unit
Read this for a description of the Instrumentation Trace Macrocell (ITM) unit.
Chapter13 Fault detection and handling
Read this for a description about how faults are detected and handled in the
Cortex-M7 Processor.
AppendixA Revisions
Read this for a description of the technical changes between released issues of this
book.
Glossary
The ARM® Glossary is a list of terms used in ARM documentation, together with definitions for
those terms. The ARM® Glossary does not contain terms that are industry standard unless the
ARM meaning differs from the generally accepted meaning.
See ARM® Glossary http://infocenter.arm.com/help/topic/com.arm.doc.aeg0014-/index.html.
Conventions
This book uses the conventions that are described in:
• Typographical conventions.
• Timing diagrams on pageviii.
• Signals on pageviii.
Typographical conventions
The following table describes the typographical conventions:
Style Purpose
italic Introduces special terminology, denotes cross-references, and citations.
bold Highlights interface elements, such as menu names. Denotes signal names. Also used for terms in descriptive
lists, where appropriate.
monospace Denotes text that you can enter at the keyboard, such as commands, file and program names, and source code.
monospace Denotes a permitted abbreviation for a command or option. You can enter the underlined text instead of the full
command or option name.
monospace italic Denotes arguments to monospace text where the argument is to be replaced by a specific value.
monospace bold Denotes language keywords when used outside example code.
<and> Encloses replaceable terms for assembler syntax where they appear in code or code fragments. For example:
LDRSB<cond> <Rt>, [<Rn>, #<offset>]
SMALL CAPITALS Used in body text for a few terms that have specific technical meanings, that are defined in the ARM glossary.
For example, IMPLEMENTATION DEFINED, IMPLEMENTATION SPECIFIC, UNKNOWN, and UNPREDICTABLE.
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Preface
Timing diagrams
The figure named Key to timing diagram conventions explains the components used in timing
diagrams. Variations, when they occur, have clear labels. You must not assume any timing
information that is not explicit in the diagrams.
Shaded bus and signal areas are UNDEFINED, so the bus or signal can assume any value within
the shaded area at that time. The actual level is unimportant and does not affect normal
operation.
Clock
HIGH to LOW
Transient
HIGH/LOW to HIGH
Bus stable
Bus to high impedance
Bus change
High impedance to stable bus
Key to timing diagram conventions
Timing diagrams sometimes show single-bit signals as HIGH and LOW at the same time and
they look similar to the bus change shown in Key to timing diagram conventions. If a timing
diagram shows a single-bit signal in this way then its value does not affect the accompanying
description.
Signals
The signal conventions are:
Signal level The level of an asserted signal depends on whether the signal is
active-HIGH or active-LOW. Asserted means:
• HIGH for active-HIGH signals.
• LOW for active-LOW signals.
Lower-case n At the start or end of a signal name denotes an active-LOW signal.
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Preface
Additional reading
This section lists publications by ARM and by third parties.
See Infocenter http://infocenter.arm.com, for access to ARM documentation.
See on ARM http://www.onarm.com, for embedded software development resources including
the Cortex Microcontroller Software Interface Standard (CMSIS).
ARM publications
This book contains information that is specific to this product. See the following documents for
other relevant information:
• ARM®v7-M Architecture Reference Manual (ARM DDI 0403).
• ARM® CoreLink™ Level 2 Cache Controller L2C-310 Technical Reference Manual
(ARM DDI 0246).
• ARM® CoreSight™ ETM-M7 Technical Reference Manual (ARM DDI 0494).
• ARM® AMBA® AXI and ACE Protocol Specification (ARM IHI 0022).
• ARM® AMBA® 3 AHB-Lite Protocol (v1.0) (ARM IHI 0033).
• ARM® AMBA® 3 ATB Protocol Specification (ARM IHI 0032).
• ARM® AMBA® 3 APB Protocol Specification (ARM IHI 0024).
• ARM® CoreSight™ SoC-400 Technical Reference Manual (ARM DDI 0480).
• ARM® CoreSight™ Architecture Specification (v2.0) (ARM IHI 0029).
• ARM® Debug Interface v5 Architecture Specification (ARM IHI 0031).
• ARM® Embedded Trace Macrocell Architecture Specification ETMv4 (ARM IHI 0064).
The following confidential books are only available to licensees:
• ARM® Cortex®-M7 Processor Integration and Implementation Manual (ARM DII 0239).
Other publications
This section lists relevant documents published by third parties:
• Test Access Port and Boundary-Scan Architecture, IEEE Standard 1149.1-2001 (JTAG).
• IEEE Standard for Binary Floating-Point Arithmetic, IEEE Standard 754-2008.
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Preface
Feedback
ARMwelcomes feedback on this product and its documentation.
Feedback on this product
If you have any comments or suggestions about this product, contact your supplier and give:
• The product name.
• The product revision or version.
• An explanation with as much information as you can provide. Include symptoms and
diagnostic procedures if appropriate.
Feedback on content
If you have comments on content then send an e-mail to [email protected]. Give:
• The title.
• The number, ARM DDI 0489B.
• The page numbers to which your comments apply.
• A concise explanation of your comments.
ARM also welcomes general suggestions for additions and improvements.
Note
ARM tests the PDF only in Adobe Acrobat and Acrobat Reader, and cannot guarantee the
quality of the represented document when used with any other PDF reader.
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