ARM® Cortex®-A72 MPCore Processor Technical Reference Manual

577 Pages·2015·3.6 MB·English

ARM® Cortex®-A72 MPCore Processor
Revision: r0p1
Technical Reference Manual
Copyright © 2014, 2015 ARM. All rights reserved.
ARM 100095_0001_02_en
ARM® Cortex®-A72 MPCore Processor

ARM® Cortex®-A72 MPCore Processor
Technical Reference Manual
Copyright © 2014, 2015 ARM. All rights reserved.
Release Information
Document History
Issue Date Confidentiality Change
0000-01 23 October 2014 Confidential First release for r0p0.
0000-02 20 February 2015 Non-Confidential First release for r0p1.
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ARM® Cortex®-A72 MPCore Processor

Unrestricted Access is an ARM internal classification.
Product Status
The information in this document is Final, that is for a developed product.
Web Address
http://www.arm.com
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Contents
ARM® Cortex®-A72 MPCore Processor Technical
Reference Manual
Preface
About this book ............................................................................................................ 9
Feedback .................................................................................................................... 12
Chapter 1 Introduction
1.1 About the Cortex-A72 processor ............................................................................ 1-14
1.2 Compliance .............................................................................................................. 1-15
1.3 Features .................................................................................................................. 1-17
1.4 Interfaces ................................................................................................................ 1-18
1.5 Implementation options .......................................................................................... 1-19
1.6 Test features ............................................................................................................ 1-20
1.7 Product documentation and design flow .................................................................. 1-21
1.8 Product revisions .................................................................................................... 1-23
Chapter 2 Functional Description
2.1 About the Cortex-A72 processor functions .............................................................. 2-25
2.2 Interfaces ................................................................................................................ 2-29
2.3 Clocking and resets ................................................................................................ 2-32
2.4 Power management ................................................................................................ 2-42
Chapter 3 Programmers Model
3.1 About the programmers model ................................................................................ 3-60
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3.2 ARMv8-A architecture concepts .............................................................................. 3-61
3.3 ThumbEE instruction set ........................................................................................ 3-69
3.4 Jazelle implementation ............................................................................................ 3-70
3.5 Memory model ........................................................................................................ 3-72
Chapter 4 System Control
4.1 About system control .............................................................................................. 4-74
4.2 AArch64 register summary ...................................................................................... 4-75
4.3 AArch64 register descriptions .................................................................................. 4-88
4.4 AArch32 register summary .................................................................................... 4-214
4.5 AArch32 register descriptions ................................................................................ 4-239
Chapter 5 Memory Management Unit
5.1 About the MMU ...................................................................................................... 5-276
5.2 TLB organization .................................................................................................. 5-277
5.3 TLB match process ................................................................................................ 5-278
5.4 Memory access sequence .................................................................................... 5-279
5.5 MMU enabling and disabling ................................................................................ 5-281
5.6 Intermediate table walk caches ............................................................................ 5-282
5.7 External aborts ...................................................................................................... 5-283
Chapter 6 Level 1 Memory System
6.1 About the L1 memory system ................................................................................ 6-285
6.2 Cache organization ................................................................................................ 6-286
6.3 L1 instruction memory system .............................................................................. 6-287
6.4 L1 data memory system ........................................................................................ 6-289
6.5 Program flow prediction ........................................................................................ 6-295
6.6 L1 RAM memories ................................................................................................ 6-298
Chapter 7 Level 2 Memory System
7.1 About the L2 memory system ................................................................................ 7-300
7.2 Cache organization ................................................................................................ 7-301
7.3 L2 RAM memories ................................................................................................ 7-307
7.4 L2 cache prefetcher .............................................................................................. 7-308
7.5 Cache coherency .................................................................................................. 7-309
7.6 Asynchronous errors ............................................................................................ 7-310
7.7 External coherent interfaces .................................................................................. 7-311
7.8 ACP ...................................................................................................................... 7-318
Chapter 8 Generic Interrupt Controller CPU Interface
8.1 About the GIC ........................................................................................................ 8-321
8.2 GIC functional description .................................................................................... 8-322
8.3 GIC programmers model ...................................................................................... 8-327
Chapter 9 Generic Timer
9.1 About the Generic Timer ...................................................................................... 9-341
9.2 Generic Timer functional description .................................................................... 9-342
9.3 Generic Timer register summary .......................................................................... 9-343
Chapter 10 Debug
10.1 About debug ........................................................................................................ 10-346
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10.2 Debug register interfaces .................................................................................... 10-348
10.3 AArch64 debug register summary ...................................................................... 10-350
10.4 AArch64 debug register descriptions .................................................................. 10-352
10.5 AArch32 debug register summary ...................................................................... 10-358
10.6 AArch32 debug register descriptions .................................................................. 10-360
10.7 Memory-mapped register summary .................................................................... 10-364
10.8 Memory-mapped register descriptions ................................................................ 10-368
10.9 Debug events ...................................................................................................... 10-382
10.10 External debug interface ...................................................................................... 10-383
10.11 ROM table .......................................................................................................... 10-386
Chapter 11 Performance Monitor Unit
11.1 About the PMU .................................................................................................... 11-398
11.2 PMU functional description .................................................................................. 11-399
11.3 AArch64 PMU register summary ........................................................................ 11-401
11.4 AArch64 PMU register descriptions .................................................................... 11-403
11.5 AArch32 PMU register summary ........................................................................ 11-408
11.6 Memory-mapped register summary .................................................................... 11-410
11.7 Memory-mapped register descriptions ................................................................ 11-413
11.8 Events .................................................................................................................. 11-430
11.9 Interrupts ............................................................................................................ 11-434
11.10 Exporting PMU events ........................................................................................ 11-435
Chapter 12 Cross Trigger
12.1 About the cross trigger ........................................................................................ 12-437
12.2 Trigger inputs and outputs .................................................................................. 12-438
12.3 CTI ...................................................................................................................... 12-439
12.4 CTM .................................................................................................................... 12-440
12.5 Cross trigger register summary .......................................................................... 12-441
12.6 Cross trigger register descriptions ...................................................................... 12-444
Chapter 13 Embedded Trace Macrocell
13.1 About ETM .......................................................................................................... 13-461
13.2 ETM trace generation options and resources ...................................................... 13-462
13.3 ETM functional description .................................................................................. 13-464
13.4 Reset .................................................................................................................. 13-465
13.5 ETM register interfaces ...................................................................................... 13-466
13.6 Register summary .............................................................................................. 13-467
13.7 Register descriptions .......................................................................................... 13-471
13.8 Interaction with debug and the Performance Monitor Unit .................................. 13-513
Chapter 14 Advanced SIMD and Floating-point
14.1 About Advanced SIMD and Floating-point .......................................................... 14-515
14.2 Programmers model for Advanced SIMD and Floating-point .............................. 14-516
14.3 AArch64 register summary .................................................................................. 14-517
14.4 AArch64 register descriptions .............................................................................. 14-518
14.5 AArch32 register summary .................................................................................. 14-527
14.6 AArch32 register descriptions .............................................................................. 14-528
Appendix A Signal Descriptions
A.1 About the signal descriptions ...................................................................... Appx-A-533
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A.2 Clock signals ................................................................................................ Appx-A-534
A.3 Reset signals .............................................................................................. Appx-A-535
A.4 Configuration signals .................................................................................. Appx-A-536
A.5 GIC CPU interface signals .......................................................................... Appx-A-538
A.6 Generic Timer signals .................................................................................. Appx-A-540
A.7 Power control signals .................................................................................. Appx-A-541
A.8 ACE and CHI interface signals .................................................................... Appx-A-543
A.9 CHI interface signals .................................................................................... Appx-A-546
A.10 ACE interface signals .................................................................................. Appx-A-551
A.11 ACP interface signals .................................................................................. Appx-A-556
A.12 Debug interface signals .............................................................................. Appx-A-559
A.13 ETM interface .............................................................................................. Appx-A-562
A.14 Cross trigger channel interface .................................................................... Appx-A-564
A.15 PMU signals ................................................................................................ Appx-A-565
A.16 DFT and MBIST signals .............................................................................. Appx-A-566
Appendix B AArch32 Unpredictable Behaviors
B.1 Unpredictable behaviors .............................................................................. Appx-B-568
B.2 Debug UNPREDICTABLE behaviors ................................................................ Appx-B-570
Appendix C Revisions
C.1 Revisions .................................................................................................... Appx-C-577
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Preface
This preface introduces the ARM® Cortex®-A72 MPCore Processor Technical Reference Manual.
It contains the following:
• About this book on page 9.
• Feedback on page 12.
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Preface
About this book
About this book
This document describes the ARM Cortex-A72 processor.
Product revision status
The rmpn identifier indicates the revision status of the product described in this book, for example, r1p2,
where:
rm Identifies the major revision of the product, for example, r1.
pn Identifies the minor revision or modification status of the product, for example, p2.
Intended audience
This document is written for system designers, system integrators, and programmers who are designing
or programming a System-on-Chip (SoC) that uses the Cortex-A72 processor.
Using this book
This book is organized into the following chapters:
Chapter 1 Introduction
This chapter introduces the Cortex-A72 processor and its features.
Chapter 2 Functional Description
This chapter describes the functionality of the Cortex-A72 processor.
Chapter 3 Programmers Model
This chapter describes the processor registers and provides information for programming the
processor.
Chapter 4 System Control
This chapter describes the System registers, their structure, operation, and how to use them.
Chapter 5 Memory Management Unit
This section describes the Memory Management Unit (MMU).
Chapter 6 Level 1 Memory System
This section describes the Level 1 (L1) memory system.
Chapter 7 Level 2 Memory System
This chapter describes the Level 2 (L2) memory system.
Chapter 8 Generic Interrupt Controller CPU Interface
This section describes the Cortex-A72 processor implementation of the GIC CPU interface.
Chapter 9 Generic Timer
This chapter describes the Cortex-A72 processor implementation of the ARM Generic Timer.
Chapter 10 Debug
This section describes the Cortex-A72 processor debug registers and shows examples of how to
use them.
Chapter 11 Performance Monitor Unit
This section describes the Performance Monitor Unit (PMU) and the registers that it uses.
Chapter 12 Cross Trigger
This chapter describes the cross trigger interfaces for the Cortex-A72 processor.
Chapter 13 Embedded Trace Macrocell
This section describes the Embedded Trace Macrocell (ETM) for the Cortex-A72 processor.
Chapter 14 Advanced SIMD and Floating-point
This chapter describes the Advanced SIMD and Floating-point features and registers in the
Cortex-A72 processor.
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Preface
About this book
Appendix A Signal Descriptions
This section describes the Cortex-A72 processor signals.
Appendix B AArch32 Unpredictable Behaviors
This appendix describes specific Cortex-A72 processor UNPREDICTABLE behaviors that are of
particular interest.
Appendix C Revisions
This appendix describes the technical changes between released issues of this book.
Glossary
The ARM Glossary is a list of terms used in ARM documentation, together with definitions for those
terms. The ARM Glossary does not contain terms that are industry standard unless the ARM meaning
differs from the generally accepted meaning.
See the ARM Glossary for more information.
Typographic conventions
italic
Introduces special terminology, denotes cross-references, and citations.
bold
Highlights interface elements, such as menu names. Denotes signal names. Also used for terms
in descriptive lists, where appropriate.
monospace
Denotes text that you can enter at the keyboard, such as commands, file and program names,
and source code.
monospace
Denotes a permitted abbreviation for a command or option. You can enter the underlined text
instead of the full command or option name.
monospace italic
Denotes arguments to monospace text where the argument is to be replaced by a specific value.
monospace bold
Denotes language keywords when used outside example code.
<and>
Encloses replaceable terms for assembler syntax where they appear in code or code fragments.
For example:
MRC p15, 0 <Rd>, <CRn>, <CRm>, <Opcode_2>
SMALL CAPITALS
Used in body text for a few terms that have specific technical meanings, that are defined in the
ARM glossary. For example, IMPLEMENTATION DEFINED, IMPLEMENTATION SPECIFIC, UNKNOWN, and
UNPREDICTABLE.
Timing diagrams
The following figure explains the components used in timing diagrams. Variations, when they occur,
have clear labels. You must not assume any timing information that is not explicit in the diagrams.
Shaded bus and signal areas are undefined, so the bus or signal can assume any value within the shaded
area at that time. The actual level is unimportant and does not affect normal operation.
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