Architectures and circuits for time- interleaved ADC's

31 Pages·2007·0.14 MB·English

Architectures and circuits for time-
interleaved ADC’s
Sandeep Gupta
Teranetics, Santa Clara, CA
Outline
• Introduction to time-interleaved architectures.
• Conventional Sampling architectures and their
application space:
– High accuracy (>7ENOB) for relatively lower
sampling speeds (<1GS/s)
– High sampling speeds, >1GS/s, up-to 20GS/s, lower
accuracy (<7 ENOB)
• Proposed architecture (ISSCC 2006) for
broader application space.
• Measured results for a 1GS/s 11 bit ADC
based on the proposed architecture.
Time-interleaved architectures
Sub-ADC
1
Sub-ADC DSP
Analog 2
input
S/H /Array of Sub-S/H’s
Sub-ADC
N
• Time interleaved architectures:
– Efficient architectures for achieving accuracy at high speed.
• Caveats: SNR limitations due to
• Gain & Offset mismatches: Present in all time-interleaved
architectures.
• Phase & bandwidth mismatch: Dominant only in some
time-interleaved architectures
Mismatch errors: Intuitive reasoning
Nyquist ADC, NOT interleaved
0 BW Fs/4 Fs/2 3*Fs/4 Fs
in
Sub-sampled ADC outputs, time-interleaved output
0 BW Fs/4 Fs/2 3*Fs/4 Fs
in
Sub-sampled ADC outputs recombined with perfectly matched array
All periodic repetitions cancel except at integer
multiples of Fs
0 BW Fs/4 Fs/2 3*Fs/4 Fs
in
Offset, gain, Phase Skew and bandwidth
mismatch
Fs/N+/- Fin
Sub-sampled ADC
outputs
0 Fin
Fs/4
Fs/2
Offset mismatch
Magnitude
independent of
Gain mismatch
signal freq.
Magnitude
Phase, bandwidth
dependent on
mismatch
signal freq.
Phase and bandwidth mismatches
• Phase mismatch:
– Systematic mismatches in clocks
• Layout ΔRC effects
• generation of sub-sampled clocks
– Random mismatch in clocks
• Jitter
• Sampling bandwidth mismatches
– Primarily due to mismatch in switch resistance,
layout ΔRC effects.
– Dominant mechanism the phase shift caused by
different sampling bandwidths.
SNDR vs. phase/bandwidth mismatch
• SNDR ~ α −20*log10(phase error)
• Phase error (jitter/skews) = 2π*fin*(σ /fs)
j
– Wherein, σ is the RMS jitter OR the standard
j
deviation of the clock skew
– fs, the sampling clock frequency
• Phase error due to sampling bandwidth
mismatch = 2π*fin*σ /f
N BW
– Wherein f is the sampling bandwidth of a
bw
normalized sub-channel.
– Wherein σ is the standard deviation of the
N
bandwidth mismatch between sub-channels.
SNDR vs. interleaving factor
• SNDR α - 10*log10[1-1/N], mismatch σ being constant.
(Ref: Seng Pan U et. al., IEEE trans. Inst. and
measurement, Aug. 2004.)
100.5
100
99.5
B) 99
d
R (
D
N
S 98.5
98
97.5
97
2 4 6 8 10 12 14 16
Amount of time interleaving (N)
• However, physically mismatches (systematic/random)
can increase with N (not taken in account in graph above)
Conventional Architectures and their
application landscape
Conventional architecture 1
p<1>, 00
Advantage:
Clock, Fs 1. Phase skews in p<i>,
Sub-ADC
Bandwidth mismatch errors,
not much loss of accuracy.
Vin
S/H p<N>, 3600*(N-1)/N
Disadvantages:
0-Fs/2
1. N/2 Sub-ADCs loading on
Sub-ADC
Held first sampler limits its BW,
performance,
Fs
• Sub-ADC sampling
p<1>
speed still high, if N kept
p<2> low.
p<3>
2. Sub-ADC input signal held
p<4> only for short time
<(T/2=1/2Fs)
Example: N=4