Apple IIgs Hardware Reference Manual

267 Pages·2009·56.22 MB·English

APPLE
PROGRAMMER'S
AND DEVELOPER'S
ASSOCIATION
290 SW 43rd. Street
Renton, WA 98055
206-251-£548
'ApplellGs
Hardware
Reference
.M anual
APDA·Draft
21 Nov., 1986
APDA#: K2SHWR

'--
Apple IIGS
Hardware Reference
APDA Draft
21 November, 1986
Apple Technical Publications
This document contains preliminary material. It does not include
• final editorial corrections
• final artwork
• an index
It may not includefinal technical changes.
W® APPLE COMPUTER,INC.
Copyright © 1986 Apple Computer. Inc. All rights reserved.
Apple lIes Hardware Reference
This manual is copyrighted by Apple orby Apple's suppliers, with all rights reserved. Under the copyright
laws, this manual may not be copied, in whole or in pan, without the written consent of Apple Computer,
Inc. This exception does not allow copies to be made for others, whether or not sold, but all of the material
purchased may be sold, given, or lent to another per.;on. Under the law, copying includes translating into
another language.
Apple Computer, Inc.
20525 Mariani Avenue
Cupertino, California 95014
[phone]
© 1986 Apple Computer, Inc.
Apple, the Apple logo, AppleTaJk, DuoDisk, ImageWriter, LaserWriter and ProDOS are registered
trademarks of Apple Computer, Inc. Apple IIGS, Apple DeskTop Bus, Macintosh, SANE and UniDisk are
trademarks of Apple Computer, Inc.
Simuhaneously published in the United StateS and Canada.
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Contents
iii Table of Contents
List of Illustrations and Tables
viii List of Illustrations
x List of Tables
xi Foreword
Chapter 1: Introduction to the Apple IIGS
1-1 Removing the cover
1-2 Peripheral expansion slots
1-2 Connectors
1-2 Two serial ports
1-3 Disk drive port
1-4 RGB video connector
1-4 Composite video conector
1-5 Apple DeskTop Bus
1-5 Game connector
1-6 A closerlook
1-7 Apple II compatibility
1-8 New features
1-9 Terminology
1-9 Memory allocation .
1-10 Summary
Chapter 2: Mega II: Maintaining Apple II Compatibility
2-2 The Mega II custom IC
2-3 The Apple lIe
2-3 RAM upgrade
2-3 Apple I/O
2-2 The keyboard
2-3 Reading the keyboard
2-6 Apple II video
2-7 Video output
2-7 Text modes
2-9 Text character sets
2-10 4O-co1umn versus SO-column text
2-12 Graphics modes
2-12 Lo-Res graphics
2-13 Hi-Res graphics
2-15 Double Hi-Res graphics
2-16 Video display pages
2-18 Display mode switching
2-20 Addressing display pages directly
2-27 The text window
2-28 Secondary inputs and outputs
2-28 The speaker
2-29 Game I/O
2-29 The hand control signals
2-30 Annunciator outputs
2-30 Switch inputs
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2-31 Analog inputs
2-31 Summary of secondary I/O'!ocations
2-32 Standard Apple II memory
2-33 Main memory map
2-34 RAM memory allocation
2-35 Reserved memory pages
2-35 Page zero
2-36 The 6502 stack
2-36 The input buffer
2-36 Link-address storage
2-36 The display buffers
2-37 Bank-switched memory
2-38 Setting bank switches
2-40 Reading bank switches
2-41 The State register
2-42 Auxiliary memory
2-44 Memory mode switching
2-46 Peripheral expansion
2-46 Selecting a device
2-46 The Slot register
2-47 Peripheral-card memory spaces
2-48 Peripheral-card I/O space
2-48 Peripheral-card ROM space
2-49 Expansion ROM space
2-51 Peripheral-card RAM space
2-51 I/O programming suggestions
2-52 Finding the slot number with ROM switched in
2-52 I/O addressing
2-53 RAM addressing
2-54 Other uses of I/O memory space
2-55 Switching I/O memory
2-56 Developing cards for slot 3
2-57 Interrupts
2-57 What is an interrupt?
Chapter 3: The FPI: New Features
3-2 The FPI subsystem
3-2 Memory allocation
3-3 The State register
3-3 Shadowing
3-5 The Shadow register
3-8 The Speed register
3-10 RAM control
3-10 ROM
3-10 I/O processing
3-10 The S lot register
3-12 Synchronization
3-13 The Mega II cycle
3-14 Mega II auxiliary bank access
3-14 Real-time clock Ie interface
Chapter 4: Video
4-1 The Video Graphics Controller
4-2 Apple II compatibility
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4-3 New video display features
4-4 Text and background color
4-4 Border color
4-4 To color or not to color ...
4-5 New graphics display modes
4-6 Super Hi-Res graphics
4-6 The Super Hi-Res graphics buffer
4-8 Scan-line control bytes ($9DOO--$9DC7)
4-9 Color palettes ($9EOO-$9FFF)
4-10 Pixels
4-11 The New-Video register
4-13 Color-Fill mode
4-13 VGC interrupts
4-14 VGC Interrupt register
4-15 VGC Interrupt-Clear register
4-16 Graphics summary
Chapter 5: Peripheral Expansion Slots
5-2 The expansion slots
5-5 Apple II compatibility
5-5 Direct memory access
5-5 I/O in the Apple IIGS
5-5 Slot I/O cards
5-6 DMA canis
5-6 Expansion slot signals
5-6 The buffered address bus
5-7 The slot data bus
.....• 5-13 Interrupt and DMA daisy chains
5-13 Loading and driving rules
5-13 S urnrnary
Chapter 6: Apple IIGS Sound
6-1 Sound synthesis
6-2 Accessing the DOC
6-3 The Sound Control register
6-4 Address Pointer register
6-5 Write operation
6-5 Read operation
6-5 Playing back the sound
6-6 The DOC registers
6-6 The Oscillator Interrupt register ($EQ)
6-7 The Oscillator Enable register ($El)
6-7 The NO Converter register ($E2)
6-7 The Oscillator Control register ($AO-$BF)
6-9 The Data register ($60--$7F)
6-9 The Volume register ($4O-$5F)
6-9 The Frequency High and Frequency Low registers ($00--$3F)
6-9 The Waveform register ($CO-$DF)
6-10 Sound input and output specifications
6-12 S urnmary
Chapter 7: Apple DeskTop Bus
7 -1 Introduction
7-2 The input bus
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7-3 The ADB microcontroller
7-3 The keyboard GLU
7-3 Keyboard GLU registers
7-3 System Status register
7 -5 Key board Data register
7-5 Modifier Key register
7-6 Mouse Data register
7 -6 Command/Status register
7 -7 Bus communication
7-8 Signals
7 -8 Attention and sync
7-8 Reset
7-9 Service request
7-9 Reset .
7- 9 Transactions
7-10 Apple DeskTop Bus peripheral devices
7 -10 Commands
7-11 Talk
7-11 Listen
7 -11 Device registers
7-11 Collision detection
7 -11 Error conditions
7 -12 Network layer (ADB types) .
7-12 Nonnal devices
7 -12 Extended sddress devices
7 -13 Register 3
7 -13 Service request
Chapter 8: The Disk Port
8-1 Introduction
8-1 Apple II compatibility
8-2 The disk port connector
8-2 TheIWM
8-3 The Disk Interface register
Chapter 9: The Memory Expansion Slot
9-1 Introduction
9-1 Extended RAM
9-2 Extended RAM Mapping
9-2 MSIZE
9-3 Ghosting
9-3 ExtendedROM
9-4 Address multiplexing
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Chapter 10: Power Supply
10-1 Introduction
. 10-1 Function
~--
10-1 Specifications
10-2 Power connector
Chapter 11: 6SC816 Microprocessor
11-1 Introduction
11-2 65C816 Features
11-3 The 16-bit 65C816
11-4 Microprocessor differences
11-4 The registers
11-5 The accumulator
11-5 X Index register
11-5 Y Index register
11-5 Data bank register
11-5 S tack pointer
11-5 Program Status register
11-5 Program counter
11-5 Program bank register
11-6 Direct register
11-6 Emulating the 6502
11-6 The e bit
11-6 The m bit
11-6 The x bit
11-7 Operating speed
11-7 Summary
11-8 65C816 data sheets
A-I Appendix A: Roadmap to the Apple IIGS Technical Manuals
B-1 Appendix B: International Keyboards
C-I Appendix C: Character Generator
D-I Appendix D: Schematic Diagrams
E-I Appendix E: Conversion Tables
107 Appendix F: Frequently Used Tables
Glossary
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List of Illustrations and Tables
List of Ilustrations
Illustration Title Page
Figure 1-1 The Apple JIos
Figure 1-2 Releasing the snaps to remove the cover
Figure 1-3 The Apple lIas with cover removed
Figure 1-4 The Apple IIos connectors
Figure 1-5 Pin configuration of a serial pon connector
Figure 1-6 Apple lIos block diagram
Figure 1-7 Bank memory map
Figure 2-1 The Apple IIos block diagram
Figure 2-2 40-column text display
Figure 2-3 80-column text display
Figure 2-4 Hi-Res display bits
Figure 2-5 Map of 40-column text display
Figure 2-6 Map of 80-column lext display
Figure 2-7 Map of Lo-Res graphics display
Figure 2-8 Map of Hi-Res graphics display
Figure 2-9 Map of Double Hi-Res graphics display
Figure 2-10 Game I/O connector
Figure 2-11 Memory for bank $EO
Figure 2-12 RAM allocation map
Figure 2-13 Bank-switChed memory map
Figure 2-14 Slate register
Figure 2-15 Memory map with auxiliary memory
Figure 2-16 Slot register
Figure 2-17 Expansion ROM enable circuit
Figure 2-18 ROM disable address decoding
Figure 2-19 I/O memory map
Figure 3-1 The Apple JIos block diagram and the FPI. ..
Figure 3-2 The Apple JIOs memory map
Figure 3-4 The Shadowed memory map
Figure 3-5 The Shadow register
Figure 3-6 The Speed register
Figure 3-7 The SIOI register
Figure 3-8 clIO cycles, 14M cycles, and M-Stales
Figure 3-9 The Control register
Figure 4-1 Block diagram of the Apple liaS and video ...
Figure 4-2 Screen Color register
Figure 4-3 Border Color register
Figure 4-4 ColorlMonochrome register
Figure 4-5 Super Hi-Res graphics display buffer
Figure 4-6 Scan-Line control byte format
Figure 4-7 Color palette format
Figure 4-8 Pixel data byte format
Figure 4-9 Color selection in 640 mode
Figure 4-10 New Video register
Figure 4-11 Scan-Line interrupt
Figure 4-12 VGC Interrupt register
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