US008832528B2 (12) United States Patent (10) Patent N0.: US 8,832,528 B2 Thatcher et al. (45) Date of Patent: *Sep. 9, 2014 (54) APPARATUS, SYSTEM, AND METHOD TO (58) Field of Classi?cation Search INCREASE DATA INTEGRITY IN A USPC ....... .. 714/766, 758, 770, 799, 805, 710, 723, REDUNDANT STORAGE SYSTEM 714/761 See application ?le for complete search history. (75) Inventors: Jonathan Thatcher, Liberty Lake, WA (US); David Flynn, Sandy, UT (US); (56) References Cited Joshua Aune, South Jordan, UT (US); U.S. PATENT DOCUMENTS Jeremy Fillingim, Salt Lake City, UT (US); Bill Inskeep, West Valley City, UT 4,633,471 A * 12/1986 Pereraet a1. ................ .. 714/758 (US); John Strasser, Syracuse, UT 4,740,968 A 4/1988 Aichelmann, Jr. (US); Kevin Vigor, Salt Lake City, UT (Continued) (Us) FOREIGN PATENT DOCUMENTS (73) Assignee: Fusion-i0, Inc., Salt Lake City, UT (US) EP 569236 11/1993 (*) Notice: Subject to any disclaimer, the term of this 61-226853 8/1986 patent is extended or adjusted under 35 (Continued) U.S.C. 154(b) by 215 days. OTHER PUBLICATIONS This patent is subject to a terminal dis claimer. Of?ce Action in Chinese Application No. 2009801280134 issued Apr. 1, 2013, 21 pages. (21) Appl. N0.: 13/321,484 (Continued) (22) PCT Filed: May 18, 2010 Primary Examiner * Fritz Alphonse (74) Attorney, Agent, or Firm * Meyertons, Hood, Kivlin, (86) PCT No.: PCT/US2010/035320 Kowert & Goetzel, PC. § 371 (0X1), (2), (4) Date: Feb. 3, 2012 (57) ABSTRACT In various embodiments, an apparatus, system, and method (87) PCT Pub. No.: WO2010/135370 may increase data integrity in a redundant storage system. In PCT Pub. Date: Nov. 25, 2010 one embodiment, a request is received for data stored at a storage system having a plurality of storage elements, Where (65) Prior Publication Data one or more of the plurality of storage elements include parity information. A determination is made that one of the plurality US 2012/0131413 A1 May 24,2012 of storage elements is unavailable, the unavailable storage element being a functional storage element and including at Related US. Application Data least a portion of the data. Responsive to the determination, (63) Continuation-in-part of application No. 12/468,041, the data is reconstructed based on at least a portion of the ?led on May 18, 2009, noW Pat. No. 8,281,227. parity information and data from one or more of the plurality of storage elements other than the unavailable storage ele (51) Int. Cl. ment; a response is provided to the request such that the G11C 29/00 (2006.01) response includes the reconstructed data. (52) US. Cl. USPC .......................... .. 714/766; 714/758; 714/805 20 Claims, 22 Drawing Sheets cuem 1.1.1 COMDMSI .142 Sella'swne Storage Devlue 102 thdrétate Siner Con?uller 1m Wme Date F) ' sounsme Storage 125 Reduction Demqu Rewnhgurahon Apparatus Apparatus Apparalus 15 LE m US 8,832,528 B2 Page 2 (56) References Cited 6,934,878 B2 8/2005 Massa et 31. 6,938,133 B2 8/2005 Johnson @131. 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Internet Article, May 19, 2004, pp. 8, XP002535765, WWW. datasheetarchive.com. * cited by examiner US. Patent Sep. 9, 2014 Sheet 1 0f 22 US 8,832,528 B2 100 Client M Client Client Computer M M Network M Computer M Solid-State Storage Device M Solid-State Storage Controller M Write Data Pipeline Solid-State Stora e M CID 1% 9 Read Data Pipeline M Reduction Detection Reconfiguration Apparatus Apparatus Apparatus M M @ FIG. 1 US. Patent Sep 9 2014 Sheet 2 0f 22 US 8,832,528 B2 ' a 200 _ g m A Storage Control Bus 212a (D “'6 T) + 4, g E glo E BankO Bank 1___ Bank N Application m *g e 32 214a 214b 214m Specific Processors 0 V0 1 _> SSS 0.0 SSS 0.1 _> SSS ON E 0 i 216a 218a 220a 6 g 8 ¢ ¢ -- o m“ a, +SSSi.O +SSSi.1 *SSSLN 5’ 216b 218b 220b Controllers ¢ E5| 0 =0 - c = c L 6 ‘ = I I I Peer M “@2805 §+ SSSM.O ,SSSMA +SSSMN 5 m 5 N g g 5 % 21 :m 22;)m ¢ 0 w .. Storage Controllers z c Solid-State Storage 110a o 51:) 4» 3 8t m I Storage Control Bus m 2 E 7‘; * Bank 0 Bank 1 Bank N 3| co U, 2 g 5 g 214a 214b 214n SB@yustse m N gogggggl ssso.o ssso.1 SSSON RCoDntMroAl N2l4e4 E M > B 3 S “g ‘ 216a 218a 220a “5 O a c c e m w 4, MiSC- Logic ‘I, + see 1.0 + sss 1.1 sss 1.N ? 5 216b 218b 220b CPUs Master 9 't ' ¢ : c *— +> Controller ° M sss M.1 sss M.N % a g ’ Siamo * 218m ’ 220m ‘5 ‘L, DMA Cntrller 5 ¢ ¢ ¢ Con4tro—ll»ers 0 E 8 Solid-State Storage 110n EMxetm.. 250 '3 Memory 3 1+ Controller 2 . 0 (Q\l a L Dynamic @N Random 9 I ¢ Memory Array 9 Static Mem. @ t 6%? (DRAM) Array T6 EMxetm.. 252 2 4+ Mgmt Mgmt Bus Solid-State % _ Controller : : E Storage Device w m (IZC) m FIG. 2 US. Patent Sep. 9, 2014 Sheet 3 0f 22 US 8,832,528 B2 300 \ /\|Buffer Control @ Data Bus & k A J\ l\ _ l\ Output Buffer Cntl Q 330 ‘ 342 ‘ " T — ) Cntl Q Input Buffer ? @ Read Program Cntl Q ‘ Module 4* 342 4 W . _ rlte Program @ O Cntl Q <l' > - > Module * 2 E 310 Alignment i’l — c Cntl Q ‘5 7 '6 MOdu'e “ ? ‘ E, , Cntl Q Compression 5 ? 8 ? Module ? 0 8 * . 01 + .6 u Decompresslon ‘ Cntl Q ‘ g , Gnu Q _ Encryption g :5 Module ? _ :2 ? Module m m E + w + 5 g Decryption ‘ Cntl Q ‘ % Garb. Collector (—5 -I MOdu'e g E E Bypass 316 * 0 4 Q 0 + _' Garb' COHGCtor O Cntl Q Packetizer Bypass ? ’ 3 302 4 _ _ . i DepaCket'zer a Gnu Q ( , Cntl Q ’ Media Encrypt. % _ ? Module ? . i MGCIIG Decrypt. ‘ Cl'i? Q ( ECC Generator Module E E 304 4 v T ECC Correction Bank lnterleave Write Buffer < > Module Controller 320 _ E E — V * t t i Read Sync. ' ' Write Sync — — — — — — — Buffer — Sync' BUHer — Buffer - — a a w E ‘ $ ‘ W 't D t “1 Read Data H e a a E Pipeline Sgra?e|:3us Pipeline O 108 on ro er 106 ? — 3E — 8g Cmontr oller I v a g V V 5 Storage "0 Bus m Storage Control Bus @ FIG. 3 US. Patent Sep. 9, 2014 Sheet 5 0f 22 US 8,832,528 B2 450 Storage Storage Storage Storage Storage Element 1 Element 2 Element 3 Element 4 Element n 402a M 4020 402d M ILEB PEB 1 PEB 2 PEB 3 PEB 4 :? 404a 4040 4040 404d - . l.__-_______ . _ _ _ _ _ _ _ _.__________ || LP Page 0 Page 0 Page 0 Page 0 || 1% _ 406a _ _ __ 4_06_b 4000 r 4090_ _ _ _ _ "CEhigk D O D 0 ' P 0 II D 0 ciigk :IL456 " 4(Ea __ _ 408b | m n 456 H D 1 P 1 D 1 D 1 || 408a 408 4080 408d ll : I I E II P m D m D m D m II 4089 408b 4080 408d l|_________- __________-_-_________ : Page 1 Page 1 Page 1 Page 1 I 410a 410b 4100 410d | D 0 D 0 D 0 D 0 | 408a 408b 4080 408d ' D 1 D 1 D 1 P 1 : 408a 408b 4080 4089 | I I I I | D m D m P m D m | 408a 408b 4089 408d l l l I Page m Page m Page m Page m I 412a M 4120 M l D o P 0 D 0 D 0 | m 4089 4080 408m l I P 1 D 1 D 1 D 1 I m M 4086 m l E E E : | D m D m D m D m | 408a m m _0§_m4 l I- _ _ _ _ _ _ _ . _ _ _ _ _ . _ _ _ _ _ . _ _ _ _ _ ._ _ _ US. Patent Sep. 9, 2014 Sheet 6 0f 22 US 8,832,528 B2 500 Reduction Apparatus E Receive Module Data Read Module E E Regeneration Module ECC Module E m FIG. 5 US. Patent Sep. 9, 2014 Sheet 7 0f 22 US 8,832,528 B2 600 Reduction Apparatus Data Read Module Receive Module g Q . Read Rotation Module m Regeneration Module ECC Module % @ ECC Check Module Substitution Module E w Device Error Periodic Read Module Determination Module m @ Parity Rotation Module ECC Correction Module m % FIG. 6
Description: