AND9173 - A 3.3‐V/20‐A Active Clamp DC‐DC Converter with NCP1565 - ON Semiconductor

14 Pages·2014·1.73 MB·English

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AND9173/D
A 3.3‐V/20‐A Active
Clamp DC‐DC Converter
with NCP1565
The NCP1565 is a new high-performance voltage or
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peak-current mode control integrated circuit dedicated to
active-clamp forward converters. Designed in a BiCMOS APPLICATION NOTE
process, the part can switch up to several MHz and offers
everything needed to build rugged and cost-effective dc-dc
converters for the telecommunication market. Available in
a QFN package, the part will equally work well with ( )
v t
aself-driven synchronous rectified output stage or with cc
( )
dedicated drivers such as the new NCP81178. This v t
outM
application note describes the part implemented in
a3.3-V/20-A quarter brick dc-dc converter implementing
self-driven synchronous MOSFETs. ( )
v t
uvlo
General Description
The part initial power is given by a high-voltage current
source delivering up to 40mA as a guaranteed minimum
current across the allowed temperature range. Once
connected to the input rail, the current source charges the
V capacitor and lifts its positive terminal to the controller
CC
start-up voltage, 9.5V. At this point, the source turns off and
the part begins to initialize. During this short period of time, Figure 1. A Typical Power-on Sequence where the
there are no output pulses. In case V falls down to 9.4V UVLO Time Constant Dictates the Moment at
CC
which the Part Starts to Pulse
the current source is turned on again and maintains V
CC
between 9.5/9.4V in a hysteretic way. This is a so-called
Dynamic Self-Supply (DSS) operation.
Once all internal flags are cleared, the current source is
turned off and the soft-start pin is released. When the
soft-start (SS) voltage passes 1.35V, the main drive output, ( )
v t
OUTM, starts to pulse. Please note that OUTA was already outM
pulled high at V equals 9.5V to pre-charge the active
CC
clamp P-channel negative bias circuitry. Figure1 shows ( )
v t
atypical power-on sequence in which the UVLO filter SS
delays the switching operations. Please note the DSS mode
until the UVLO level gives the green light to pulse. ( )
d t
Thesmall leap on the UVLO signal illustrates the hysteresis
action.
Figure2 offers a different view of the start-up sequence
and in particular, the duty ratio evolution along the soft-start
rising voltage. Please note that pulses appear after the SS
Figure 2. It is Possible to Monitor the Duty Ratio
voltage exceeds 1.35V. Evolution During the Soft-start Sequence
© Semiconductor Components Industries, LLC, 2014 1 Publication Order Number:
July, 2014 − Rev. 0 AND9173/D
AND9173/D
In this example, the auxiliary winding takes over after
several switching cycles. In case it does not happen,
e.g.because the primary-side rectification diode is broken,
the current source will reactivate and will maintain the V
CC
voltage, self-supplying the controller until a proper auxiliary
voltage takes over. It is important to insist on power
dissipation in this mode as the current absorbed by the
high-voltage pin (22) is roughly the average current
consumed by the part. This current depends on the part
internal consumption and the driver current. The part, alone,
consumes around 5mA. Assume you drive a 50-nC Q
G
MOSFET at a 300-kHz switching frequency. In this case,
thecurrent consumed from the driver is
Figure 3. This Transient Thermal Resistance can
I (cid:2)F (cid:3)Q (cid:2)300k(cid:3)50n(cid:2)15mA (eq. 1) be Used to Check the Peak Power Capability of
drv SW G
the QFN Package. T is 25(cid:2)C for this Chart
A
which added to the 5-mA consumption makes 20mA. If the
part is biased from a 72-Vdc source, the controller will The chart tells you that a 50-mA average current can be
roughly dissipate 1.5W. Needless to say that in lack of consumed from the 72-V input during 1s at a 25-°C ambient
awide and thick dissipative copper area, the part temperature. From this value, we can rederive the transient
temperature will quickly rise, potentially destroying the die thermal resistance obtained from simulation.
as the internal shutdown cannot stop the DSS. For a QFN 150(cid:4)25
package mounted on a 4-layer PCB together with r(t)(cid:2) (cid:2)34.7oC(cid:5)W (eq. 4)
50m(cid:3)72
a100-mm2 35-(cid:2)m copper area, the junction-to-ambient
thermal resistance is evaluated to 48°C/W. If we consider Now, at a 70-°C ambient temperature, during 1s,
amaximum junction temperature of 110°C at a 70-°C themaximum power the part will safely dissipate is equal to
ambient temperature, the part will be able to dissipate
150(cid:4)70
amaximum power of P (cid:2) (cid:2)2.3W (eq. 5)
max
34.7
P (cid:2)Tj,max(cid:4)TA(cid:2)100(cid:4)70(cid:2)833mW (eq. 2) or a 32-mA current from the 72-V input line.
max
R 48
(cid:3)JA
The part is able to issue a status via its dual-function
Therefore, a permanent DSS mode is only acceptable when
dedicated pin, FLT/SDN. When observed, the pin is low to
the part enters skip cycle in a deep no-load discontinuous
signal a problem or a working sequence in progress. As an
mode (in lack of synchronous rectification for instance)
example, if the soft-start pin is shorted to ground, all pulses
where the total consumption is reduced via hysteretic
are immediately stopped and the fault is signaled via the
operation. The total consumption according to Eq.2 must
assertion of the FLT/SDN pin. This is what you can see in
remain below
Figure4.
I (cid:2) Pmax (cid:2)0.833(cid:2)11.6mA (eq. 3)
DSS,max V 72
in,max ( )
v t
In case the V capacitor is purposely selected of small outM
CC
value, the DSS can be solicited for a few tens of ms until the ( )
v t
auxiliary takes over at start up. The peak power dissipated outA
in this mode must remain within the package power
dissipation capability. In this case, we need the transient
( )
thermal resistance r(t) as plotted in the below chart for T v t
A shtdwn
equals 25°C, a maximum junction temperature of 150°C and
( )
an input voltage of 72V. v t
SS
Figure 4. If the SS Pin is Shorted to Ground,
All Pulses are Stopped and the FLT/SDN is
Asserted Low to Signal the Fault
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AND9173/D
NCP1565 includes a protection against short circuit or reaching this goal, significantly improving the situation in
overload that is of auto recovery nature. An internal circuitry moderate to light load conditions.
reconstructs the dc output current by sampling and Loop control requires current injection in the feedback
averaging the primary-side current during the on time. pin. Injecting current reduces the duty ratio. When this
When this voltage image exceeds 300mV, the capacitor current exceeds 850(cid:2)A, the duty ratio hits 0% and the
connected to the RES pin (restart), begins to charge with controller skips cycles. With a synchronous rectifier, this
a20-(cid:2)A current source. While charging, should the detected situation never happens since the output inductor current
fault disappear, e.g. the voltage on the CS pin passes below remains continuous, even in a no-load situation. The duty
300mV, the 20-(cid:2)A current source stops and the capacitor is ratio will remain almost constant across the load range at
discharged via a 5-(cid:2)A source to ground. When the fault agiven input voltage. On the opposite, with a classical set of
comes back, charging resumes and the capacitor voltage diodes in the secondary side, Discontinuous Conduction
grows. When touching the 1-V threshold, all pulses stop and Mode (DCM) will happen in light or no-load operation. This
the part remains silent for 32 charge/discharge cycles of the situation will naturally induce skip cycle operation in the
RES capacitor. This is what Figure5 illustrates. At the end primary side.
of the 32 cycles, the part attempts to re-start but if the fault In presence of narrow pulses randomly distributed, typical
it still present, hiccup continues. Should the fault disappear, of skip operation, it is very likely that the auxiliary V
CC
the converter will resume operations. collapses. In this case, the internal DSS will take over and
maintain the controller dc supply around 7.5V. As this
operation can last a certain time, it is the designer duty to
( ) make sure that the average power dissipation in worst case
v t
outM (high input voltage, highest MOSFET Q ), keeps the
G
controller die temperature below a safe limit. Figure6
( )
v t displays a typical operation when skip cycle is entered in
outA
no-load (V =36V, I =0A)
in out
()
out t
32 cycles M
()
1 V out t
( ) A
v t
RES
7.5 V
Figure 5. The Part Enters a Safe Auto-recovery ()
v t
Hiccup Mode when a Fault is Detected cc
The controller also hosts a pulse-by-pulse current limit set
to 450mV which terminates a pulse in progress in case this
limit is exceeded. Finally, in case an overcurrent is sensed
for two consecutive clock cycles, e.g. because the
Figure 6. In Skip Mode, the DSS Takes Over the
secondary-side winding is accidentally shorted, the part V Rail which Collapses Given Narrow Drive
CC
immediately stops and enters the auto-restart mode. Pulses
An important feature of NCP1565 lies in its capability to
adjust the dead time in relationship to the load and the input
The Application Circuit
voltage. As the load is getting lighter, the dead time will
We have designed a 500-kHz 36-72-V dc-dc converter
expand to help reach quasi ZVS at turn on. At full load, it is
delivering 3.3V with a nominal output current of 20A.
difficult to switch on again at a drain voltage below V . This
in
Over current cutoff happens at I is 25A in our prototype.
is because the magnetizing current conflicts with the out
The board is laid out to a quarter brick dimensions and its
reflected output current N.i (t) that appears in the primary
L
electric plugs are compatible with off-the-shelf modules.
side as soon as the drain drops below V . In light load,
in
The primary side section appears in Figure7 while the
however, as I has decreased, it is possible to force the
out
secondary side is drawn in Figure8.
drain fall well below V . The adaptive dead time helps
in
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AND9173/D
L3 D2a
Vcc 660uH BAV23CL
DO1606CT−684 2
DUAL
SOT23
C31 D2b
1uF BAV23CL 1.1
M31il0l−4M−2a−x00−80−00−00−08−0R106 CC11221100CC222255MM11RRAACCTTUU 2
J1a CC11221100CC222255MM11RRAACCTTUU Vin
36−75 V +
MS5S1038−152NL 4.3
L1
1.5uH C1 C2 C3 C4 R1
51k R10 D8 7
ENJ1b 29 Gclorosuep t oo ft hceo mICponents CS 100 MMSD914 4
23 22
M3J11il0lc−4M−2a−x00−80−00−00−08−0JJ33ba ojunm/opfefr R753k R1045 R2k4 C101n6F R7.352 R101k834. .21
0 V − 100 V R40 T2 21
Mill−Max 2.2 CT02
3104−2−00−80−00−00−08−0
UN1CP1565 1C00.4100u VF R1k9 C0.113uF Pdrive R2.329 26Q2 25C26
QFN264 ramVps2c4l1amp2N3C 2V2in202N1C 2N0C U1V9L11O98REFA 18 R101k727 SIROF−68217 R12M0109e Vg
7 SS 2 17FLT/SD 17
Fault
89 DDLTMT43 1156POGUTnAd 16 DM4MSD914 Ndrive
10 RT 5 NCP1565 14OUTM 14
AGnd6 13Vcc Vcc Q1
C24 C14 R5 R8 R31 co7mp r8es N9C 1C0S 1R1ef O1T2P FDMS2572
390pF22nF 13k 66k 19.8k Power 56
11 12 13 R101k6
DT limit 500 kHz Vref
63% Vref
R35 CS C104 C7
Vref open R46 0.1uF 1uF
33k close close to U1
to U1
28
R121k3 Cop3e3n R11
499
31
DR1e1d LED C32 C28 C11 C8 Vref R34 30
Lit when fault 1.5nF10nF330pF0.1uF 499
32
Fault
Figure 7. The Primary Side of the Active-clamp Forward Uses a P-channel Transistor
The input line first goes through an EMI filter made of level to define the input voltage at which the converter
asimple damped LC filter. Some resonance can occur at starts to pulse and the level at which it stops.
high frequency and potentially affect the transfer function in Theformulas are as follows:
a wide-bandwidth design. Damping is possible via the V (cid:4)V
addition of a large electrolytic capacitor connected across R (cid:2) on off (eq. 6)
upper
I
C1,2,3,4. As its ESR is naturally larger than that of the hyst
Multi-Layer Capacitors (MLC), it will provide an efficient
R (cid:3)V
natural ac damping. Check that its ESR changes at high R (cid:2) upper enable (eq. 7)
temperature are still compatible with the required damping. lower Venable(cid:4)Voff
Damping can also be provided by the parallel resistor R .
6
For a 34-V turn-on voltage and a turn off at 33V, the upper
The input voltage splits in several paths then:
• and lower resistances (R1 and R4) must respectively be
One goes to the controller VIN pin. It biases the DSS 50k(cid:4) and 1.9k(cid:4).
circuitry and provides energy to the chip a) at start up •
Another path is the PWM sawtooth generation.
b) when the auxiliary winding disappears in deep DCM.
Theconnection of resistance R to the input rail
Please note the insertion of a small RC network made 3
provides natural feedforward operation by modifying
of R C that provides additional filtering in case of
45 40
C charging current on the fly as the input voltage
surge events. 24
varies. This alters the PWM block small-signal gain and
•
The second undergoes a division by R /R to feed the
1 4 helps getting rid of V in the final transfer function dc
in
controller undervoltage lockout pin. You will adjust this
gain expression.
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AND9173/D
To the controller left, you find all the timing components The secondary side implements a type 3 compensator,
such as switching frequency and dead time settings. Board directly driving the optocoupler LED whose anode goes to
layout around these elements is critical and their grounds a stable voltage. The auxiliary V is provided by a simple
CC
must return to the controller analog GND via the shortest bipolar ballast whose role is to provide a regulated rail but
path. also a V ac-decoupled feedback bias for the optocoupler
out
NCP1565 directly drives one low-r MOSFETs Q . LED. Failure to perfectly ac-isolate this point from V
DS(on) 1 out
The clamp section is built around a P-channel MOSFET Q creates an unwanted fast lane which hampers the phase boost
2
that is referenced to ground. You could also use an brought by the type 3 arrangement. The bipolar stage brings
N-channel type and hook it to the upper rail but a more a first rejection barrier while the added TL431 in active
complex driving circuitry would be necessary. Zener configuration brings rejection further down: the LED
Theprimary-side current sense signal is delivered by ac current must be solely be imposed by the op amp and not
transformer T , further demagnetized by D and R . by V . To extend the crossover frequency, we have
2 8 18 out
Theauxiliary voltage is provided by a buck converter purposely compensated the optocoupler pole via R and
28
supplied by the auxiliary winding. Different structures for C .
103
this auxiliary section can be envisaged without problem. The auxiliary V is obtained by a direct rectification of
CC
Synchronous rectification is accomplished by paralleling forward and flyback voltages. It is important that this
MOSFETs. Active Clamp Forward (ACF) represents the auxiliary supply comes up quickly at power on so that the
perfect structure for self-driven rectifiers. By forcing the secondary stage takes the lead immediately and imposes
magnetizing current circulation along the entire switching asoft voltage output rise through a soft-start on the op amp
period, the drive voltage is always present in the secondary reference pin.
side. 2.2-(cid:4) resistances are inserted in series with the gate
signal and damp parasitic elements present in the driving
path.
R29b close to
2.2 Q5/Q6
R2.229a gates L02.5uH 220 uF Kemet x 4 T520V227M004ATE007 JM322il3al−1M−2a−x00−01−00−00−08−0
+ 3.3 V/30 A
Q5 Payton
.3289 1R2.223a R2.223bR102k4a SNOT−MR180L2Fk4Sb4982NFR1025k5a R1602k5b cQlo5s/Qe 6to 21R2.1200C1n1F00 7C17 C18 C19 C20 R13407 JM3S21i+bl0l−4M−S2ae−x0n0s−e8 0+−00−00−08−0
QNT3MFS4982NF R101 QNT6MFS4982NF Power GND TT552200VV222277MM000044AATTEE000077 J2c
SO−8L4 222C.21cQ0l1o3s/Qe 4to SO−8L T520V227M004ATE007 ac sweepB R2 23 M31il0l−4M−T2rai−xm00−80−00−00−08−0
1nF connections 10
Mill−Max
Q4 A 8 3104−2−00−80−00−00−08−0
NTMFS4982NF S−Sense −
SO−8L C41 J2d
12nF 0 V
0K.e2m2ueFt / 200 V ULM48261 C0.2353uF R8220 colpo saem tpo R103k3 R1.350k9 R1312 11 JM322−il3el−1M−2a−xR00T−N01−00−00−08−0
C103 17 R21 C29
10nF Vcc 162 47nF R15
0
Power GND 18 R91208 C1cl0o1sn5eF to1 6U4 VVCE1EC4 C013.61uF sSeSc. R221k4 10 R1k22 12
C37
0.1uF Quiet GND 19
16V
7 to 12 V Q2SNO72T2−2223 4.3 V Vcc Vcc DM9MSD914
DM3BR1302T0G C0.318uF R27206 25 C0.110uF 2.45 V 24R27306 C0.91uFR107kC1n9F9 12 ULSM5O4T0−4213DIM3−1.2
DM6BR130TG D1N1751 CN5C R1027
Quiet GND
U3
TL431QDBVR
SOT−23
Figure 8. The Secondary Side Implements a Dual Op Amp with a Separate Reference Voltage
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AND9173/D
For a monotonic output voltage rise, capacitor C and ones, via the 0-(cid:4) series resistor R . Reference1 gives
6 15
resistance R soft-start the reference voltage at pin (+) of details on how to compensate the op amp for a particular
14
U . This forces the secondary side to take over control crossover frequency selection.
4
during the start-up sequence and impose the output voltage
shape via this network. This is the reason why the auxiliary Operational Results
These components have been assembled on a quarter
V must come up quickly, hence a rather low value for C .
CC 37
brick 6-layer PCB whose pictures appears in Figure9.
PCB routing distinguishes two grounds, noisy and quiet
Figure 9. The 100-W Converter Fits in a Compact 6-layer Quarter Brick PCB Size
Below are some operational oscilloscope shots captured at different bias points:
() ()
v t v t
out out
Figure 10. Start-up Sequence at a 20-A Output Figure 11. Start-up Sequence at a 0-A Output
Current, Vin is 48V Current, Vin is 48V
( ) ( )
v t v t
out out
40mV 20mV
Vin = 36V, Iout = 15 to 20A, 1A/(cid:2)s Vin = 48V, Iout = 15 to 20A, 1A/(cid:2)s
Figure 12. Transient Response for Two Different Configurations, Low and Nominal Line
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AND9173/D
( )
v t
DS
( )
DT2 out t DT1
M
( )
out t
A
Figure 13. The Adaptive Dead Time Helps Obtain Quasi-ZVS at a Low Operating Current. V = 72V, I = 3A
in out
Efficiency results appear below for a constant output
current of 20A:
V = 36V η = 90.88%
in
V = 48V η = 90.65%
in
V = 72V η = 88.65%
in
( )
(cid:6)
T f
( ) (cid:2) =
60
T f
m
=
f 30kHz
c
Figure 14. Open-loop AC Sweep at a 36-V Input Voltage. A 30-kHz Crossover Frequency
is Measured Together with a 60(cid:2) Phase Margin
Several open-loop measurements have been performed on Reference
this board using the series resistance R across which an ac [1] Christophe Basso, “Designing Control Loops for
2
signal is injected. One typical result at a 36-V input voltage Linear and Switching Power Supplies: A Tutorial
is given in Figure14 where a comfortable crossover Guide”, Artech House, Boston 2012, ISBN-13:
frequency of 30kHz is observed. The phase margin is also 978-1-60807-557-7
good with 60° with the absence of conditional stability [2] http://www.paytongroup.com/
zones. [3] http://www.icecomponents.com/
The author wishes to thank Payton and ICE Components
for kindly providing samples for power magnetics and the
current sense transformer.
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AND9173/D
PCB ASSEMBLY
Figure 15. Primary-side Components Assembly
Figure 16. Secondary-side Components Assembly
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AND9173/D
Figure 17. Primary-side Layer 1
Figure 18. Layer 2, Ground Plane
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